frequency.map.eqn

CPLD控制交通灯程序

-- Copyright (C) 1991-2006 Altera Corporation
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B2_7 is 74390:1|7
B2_7_reg_input = VCC;
B2_7 = TFFE(B2_7_reg_input, !GLOBAL(clk4m), , , );


--B2_6 is 74390:1|6
B2_6_reg_input = VCC;
B2_6 = TFFE(B2_6_reg_input, B2L5, , , );


--B2L5 is 74390:1|20~7
B2L5 = EXP(!B2_3 & B2_7);


--B2_5 is 74390:1|5
B2_5_reg_input = VCC;
B2_5 = TFFE(B2_5_reg_input, !B2_6, , , );


--B2_3 is 74390:1|3
B2_3_p1_out = !B2_3 & B2_5 & B2_6;
B2_3_or_out = B2_3_p1_out;
B2_3_reg_input = B2_3_or_out;
B2_3 = DFFE(B2_3_reg_input, !B2_7, , , );


--B2_34 is 74390:1|34
B2_34_reg_input = VCC;
B2_34 = TFFE(B2_34_reg_input, !B2_3, , , );


--B2_33 is 74390:1|33
B2_33_reg_input = VCC;
B2_33 = TFFE(B2_33_reg_input, B2L6, , , );


--B2L6 is 74390:1|29~7
B2L6 = EXP(!B2_31 & B2_34);


--B2_32 is 74390:1|32
B2_32_reg_input = VCC;
B2_32 = TFFE(B2_32_reg_input, !B2_33, , , );


--B2_31 is 74390:1|31
B2_31_p1_out = !B2_31 & B2_33 & B2_32;
B2_31_or_out = B2_31_p1_out;
B2_31_reg_input = B2_31_or_out;
B2_31 = DFFE(B2_31_reg_input, !B2_34, , , );


--B1_7 is 74390:2|7
B1_7_reg_input = VCC;
B1_7 = TFFE(B1_7_reg_input, !B2_31, , , );


--B1_6 is 74390:2|6
B1_6_reg_input = VCC;
B1_6 = TFFE(B1_6_reg_input, B1L5, , , );


--B1L5 is 74390:2|20~7
B1L5 = EXP(!B1_3 & B1_7);


--B1_5 is 74390:2|5
B1_5_reg_input = VCC;
B1_5 = TFFE(B1_5_reg_input, !B1_6, , , );


--B1_3 is 74390:2|3
B1_3_p1_out = !B1_3 & B1_5 & B1_6;
B1_3_or_out = B1_3_p1_out;
B1_3_reg_input = B1_3_or_out;
B1_3 = DFFE(B1_3_reg_input, !B1_7, , , );


--B1_34 is 74390:2|34
B1_34_reg_input = VCC;
B1_34 = TFFE(B1_34_reg_input, !B1_3, , , );


--4 is 4
4_reg_input = VCC;
4 = TFFE(4_reg_input, B1_34, , , );


--5 is 5
5_or_out = 4;
5_reg_input = 5_or_out;
5 = TFFE(5_reg_input, B1_34, , , );


--B1_33 is 74390:2|33
B1_33_reg_input = VCC;
B1_33 = TFFE(B1_33_reg_input, B1L6, , , );


--B1L6 is 74390:2|29~7
B1L6 = EXP(!B1_31 & 5);


--B1_32 is 74390:2|32
B1_32_reg_input = VCC;
B1_32 = TFFE(B1_32_reg_input, !B1_33, , , );


--B1_31 is 74390:2|31
B1_31_p1_out = !B1_31 & B1_33 & B1_32;
B1_31_or_out = B1_31_p1_out;
B1_31_reg_input = B1_31_or_out;
B1_31 = DFFE(B1_31_reg_input, !5, , , );


--B3_7 is 74390:3|7
B3_7_reg_input = VCC;
B3_7 = TFFE(B3_7_reg_input, !B1_31, , , );


--B3_6 is 74390:3|6
B3_6_reg_input = VCC;
B3_6 = TFFE(B3_6_reg_input, B3L5, , , );


--B3L5 is 74390:3|20~7
B3L5 = EXP(!B3_3 & B3_7);


--B3_5 is 74390:3|5
B3_5_reg_input = VCC;
B3_5 = TFFE(B3_5_reg_input, !B3_6, , , );


--B3_3 is 74390:3|3
B3_3_p1_out = !B3_3 & B3_5 & B3_6;
B3_3_or_out = B3_3_p1_out;
B3_3_reg_input = B3_3_or_out;
B3_3 = DFFE(B3_3_reg_input, !B3_7, , , );


--B3_34 is 74390:3|34
B3_34_reg_input = VCC;
B3_34 = TFFE(B3_34_reg_input, !B3_3, , , );


--B3_33 is 74390:3|33
B3_33_reg_input = VCC;
B3_33 = TFFE(B3_33_reg_input, B3L6, , , );


--B3L6 is 74390:3|29~7
B3L6 = EXP(!B3_31 & B3_34);


--B3_32 is 74390:3|32
B3_32_reg_input = VCC;
B3_32 = TFFE(B3_32_reg_input, !B3_33, , , );


--B3_31 is 74390:3|31
B3_31_p1_out = !B3_31 & B3_33 & B3_32;
B3_31_or_out = B3_31_p1_out;
B3_31_reg_input = B3_31_or_out;
B3_31 = DFFE(B3_31_reg_input, !B3_34, , , );


--clk4m is clk4m
--operation mode is input

clk4m = INPUT();


--clk1k is clk1k
--operation mode is output

clk1k = OUTPUT(4);


--clk1 is clk1
--operation mode is output

clk1 = OUTPUT(B3_31);