📄 fenei.fit.eqn
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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L11Q is numb[0]~reg0 at LC5
A1L11Q_or_out = numin[0];
A1L11Q_reg_input = A1L11Q_or_out;
A1L11Q = DFFE(A1L11Q_reg_input, GLOBAL(clock), , , );
--A1L6Q is numa[1]~reg0 at LC6
A1L6Q_p1_out = !numin[2] & !numin[3];
A1L6Q_or_out = A1L6Q_p1_out # !numin[4];
A1L6Q_reg_input = !(A1L6Q_or_out);
A1L6Q = DFFE(A1L6Q_reg_input, GLOBAL(clock), , , );
--A1L15Q is numb[2]~reg0 at LC8
A1L15Q_p1_out = !numin[3] & !numin[4] & numin[2];
A1L15Q_p2_out = !numin[4] & numin[2] & numin[1];
A1L15Q_p3_out = numin[3] & numin[4] & !numin[2];
A1L15Q_p4_out = numin[4] & !numin[2] & !numin[1];
A1L15Q_or_out = A1L15Q_p1_out # A1L15Q_p2_out # A1L15Q_p3_out # A1L15Q_p4_out;
A1L15Q_reg_input = A1L15Q_or_out;
A1L15Q = DFFE(A1L15Q_reg_input, GLOBAL(clock), , , );
--A1L4Q is numa[0]~reg0 at LC11
A1L4Q_p0_out = numin[4] & numin[3];
A1L4Q_p1_out = !numin[1] & !numin[2] & !numin[4];
A1L4Q_p2_out = !numin[2] & !numin[4] & !numin[0];
A1L4Q_p3_out = !numin[4] & !numin[3];
A1L4Q_p4_out = numin[2] & numin[4];
A1L4Q_or_out = A1L4Q_p0_out # A1L4Q_p1_out # A1L4Q_p2_out # A1L4Q_p3_out # A1L4Q_p4_out;
A1L4Q_reg_input = !(A1L4Q_or_out);
A1L4Q = DFFE(A1L4Q_reg_input, GLOBAL(clock), , , );
--A1L13Q is numb[1]~reg0 at LC13
A1L13Q_p2_out = numin[1] & numin[3] & !numin[4] & numin[0];
A1L13Q_p3_out = numin[3] & !numin[4] & numin[2];
A1L13Q_p4_out = !numin[3] & numin[4] & !numin[2];
A1L13Q_or_out = A1L13Q_p2_out # A1L13Q_p3_out # A1L13Q_p4_out;
A1L13Q_reg_input = numin[1] $ A1L13Q_or_out;
A1L13Q = DFFE(A1L13Q_reg_input, GLOBAL(clock), , , );
--A1L17Q is numb[3]~reg0 at LC14
A1L17Q_p1_out = numin[2] & numin[3] & numin[4];
A1L17Q_p2_out = !numin[2] & numin[3] & !numin[4] & !numin[1];
A1L17Q_p3_out = !numin[2] & numin[3] & !numin[4] & !numin[0];
A1L17Q_p4_out = !numin[2] & !numin[3] & numin[4] & numin[1];
A1L17Q_or_out = A1L17Q_p1_out # A1L17Q_p2_out # A1L17Q_p3_out # A1L17Q_p4_out;
A1L17Q_reg_input = A1L17Q_or_out;
A1L17Q = DFFE(A1L17Q_reg_input, GLOBAL(clock), , , );
--~GND~0 is ~GND~0 at LC16
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;
--~GND~1 is ~GND~1 at LC3
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;
--clock is clock at PIN_83
--operation mode is input
clock = INPUT();
--numin[0] is numin[0] at PIN_61
--operation mode is input
numin[0] = INPUT();
--numin[1] is numin[1] at PIN_81
--operation mode is input
numin[1] = INPUT();
--numin[2] is numin[2] at PIN_33
--operation mode is input
numin[2] = INPUT();
--numin[3] is numin[3] at PIN_52
--operation mode is input
numin[3] = INPUT();
--numin[4] is numin[4] at PIN_80
--operation mode is input
numin[4] = INPUT();
--numa[2] is numa[2] at PIN_4
--operation mode is output
numa[2] = OUTPUT(~GND~0);
--numa[3] is numa[3] at PIN_12
--operation mode is output
numa[3] = OUTPUT(~GND~1);
--numb[0] is numb[0] at PIN_11
--operation mode is output
numb[0] = OUTPUT(A1L11Q);
--numa[1] is numa[1] at PIN_10
--operation mode is output
numa[1] = OUTPUT(A1L6Q);
--numb[2] is numb[2] at PIN_9
--operation mode is output
numb[2] = OUTPUT(A1L15Q);
--numa[0] is numa[0] at PIN_8
--operation mode is output
numa[0] = OUTPUT(A1L4Q);
--numb[1] is numb[1] at PIN_6
--operation mode is output
numb[1] = OUTPUT(A1L13Q);
--numb[3] is numb[3] at PIN_5
--operation mode is output
numb[3] = OUTPUT(A1L17Q);
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