hghm.vhw

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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2i
--  \   \         Application : ISE
--  /   /         Filename : hghm.vhw
-- /___/   /\     Timestamp : Mon Sep 08 10:22:14 2008
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: hghm
--Device: Xilinx
--

LIBRARY IEEE;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE IEEE.STD_LOGIC_1164.All;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE STD.TEXTIO.ALL;

ENTITY hghm IS
END hghm;

ARCHITECTURE testbench_arch OF hghm IS
    COMPONENT fa
        PORT (
            a : In STD_LOGIC;
            b : In STD_LOGIC;
            c : In STD_LOGIC;
            sum : Out STD_LOGIC;
            carry : Out STD_LOGIC
        );
    END COMPONENT;

    SIGNAL a : STD_LOGIC := '0';
    SIGNAL b : STD_LOGIC := '0';
    SIGNAL c : STD_LOGIC := '0';
    SIGNAL sum : STD_LOGIC := '0';
    SIGNAL carry : STD_LOGIC := '0';

    constant PERIOD : time := 200 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 100 ns;

    BEGIN
        UUT : fa
        PORT MAP (
            a => a,
            b => b,
            c => c,
            sum => sum,
            carry => carry
        );

        PROCESS    -- clock process for a
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                a <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                a <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  185ns
                WAIT FOR 185 ns;
                b <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  385ns
                WAIT FOR 200 ns;
                b <= '0';
                c <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  585ns
                WAIT FOR 200 ns;
                c <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  785ns
                WAIT FOR 200 ns;
                b <= '1';
                -- -------------------------------------
                WAIT FOR 415 ns;

            END PROCESS;

    END testbench_arch;