adder1bit.v

来自「一位全加器」· Verilog 代码 · 共 6 行

module   Adder1Bit  (A, B, Cin, Sum, Cout) ;
	input      A, B, Cin;
	output   Sum, Cout;
	assign   Sum = (A ^ B ) ^ Cin;
	assign   Cout=(A&Cin)|(B&Cin)|(A&B);
endmodule