📄 controller.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity controller is
port
(clk:in std_logic;
hold:in std_logic;
num:buffer integer range 0 to 49;
a1,b1:out integer range 0 to 25;
red1,green1,yellow1:out std_logic;
red2,green2,yellow2:out std_logic;
shanshuo:out std_logic);
end;
architecture b_controller of controller is
begin
process(clk)
begin
if falling_edge(clk) then
if hold='1' then
red1<='1';
red2<='1';
green1<='0';
green2<='0';
yellow1<='0';
yellow2<='0';
shanshuo<='1';
else
shanshuo<='0';
if num<=19 then
a1<=20-num;
green1<='1';
red1<='0';
yellow1<='0';
elsif (num>19 and num<=24) then
a1<=25-num;
yellow1<='1';
red1<='0';
green1<='0';
else
a1<=50-num;
red1<='1';
green1<='0';
yellow1<='0';
end if;
if num<=24 then
b1<=25-num;
red2<='1';
green2<='0';
yellow2<='0';
elsif (num>24 and num<=44) then
b1<=45-num;
green2<='1';
yellow2<='0';
red2<='0';
else
b1<=50-num;
yellow2<='1';
red2<='0';
green2<='0';
end if;
end if;
end if;
end process;
end b_controller;
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