jiaotongdeng.map.rpt

用VHDL做的交通灯设计

; jiaotongdeng.bdf                 ; yes             ; User Block Diagram/Schematic File  ; E:/jiaotongdeng/jiaotongdeng.bdf ;
+----------------------------------+-----------------+------------------------------------+----------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 37      ;
; Total combinational functions     ; 35      ;
;     -- Total 4-input functions    ; 17      ;
;     -- Total 3-input functions    ; 6       ;
;     -- Total 2-input functions    ; 6       ;
;     -- Total 1-input functions    ; 6       ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 10      ;
; Total logic cells in carry chains ; 6       ;
; I/O pins                          ; 15      ;
; Maximum fan-out node              ; Clk     ;
; Maximum fan-out                   ; 10      ;
; Total fan-out                     ; 145     ;
; Average fan-out                   ; 2.79    ;
+-----------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------+
; |jiaotongdeng              ; 37 (0)      ; 10           ; 0           ; 15   ; 0            ; 27 (0)       ; 2 (0)             ; 8 (0)            ; 6 (0)           ; |jiaotongdeng                 ;
;    |controller:inst|       ; 22 (22)     ; 4            ; 0           ; 0    ; 0            ; 18 (18)      ; 2 (2)             ; 2 (2)            ; 0 (0)           ; |jiaotongdeng|controller:inst ;
;    |counter:inst1|         ; 15 (15)     ; 6            ; 0           ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 6 (6)            ; 6 (6)           ; |jiaotongdeng|counter:inst1   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; State Machine - |jiaotongdeng|controller:inst|State  ;
+----------+----------+----------+----------+----------+
; Name     ; State.s3 ; State.s2 ; State.s1 ; State.s0 ;
+----------+----------+----------+----------+----------+
; State.s0 ; 0        ; 0        ; 0        ; 0        ;
; State.s1 ; 0        ; 0        ; 1        ; 1        ;
; State.s2 ; 0        ; 1        ; 0        ; 1        ;
; State.s3 ; 1        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 10    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 10    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |jiaotongdeng|counter:inst1|Num[5]     ;
; 8:1                ; 4 bits    ; 20 LEs        ; 12 LEs               ; 8 LEs                  ; No         ; |jiaotongdeng|controller:inst|Select~0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/jiaotongdeng/jiaotongdeng.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Tue Apr 08 11:40:56 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-counter_architecture
    Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file controller.vhd
    Info: Found design unit 1: controller-controller_architecture
    Info: Found entity 1: controller
Info: Found 1 design units, including 1 entities, in source file jiaotongdeng.bdf
    Info: Found entity 1: jiaotongdeng
Info: Elaborating entity "jiaotongdeng" for the top level hierarchy
Info: Elaborating entity "controller" for hierarchy "controller:inst"
Info: Elaborating entity "counter" for hierarchy "counter:inst1"
Info: State machine "|jiaotongdeng|controller:inst|State" contains 4 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|jiaotongdeng|controller:inst|State"
Info: Encoding result for state machine "|jiaotongdeng|controller:inst|State"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "controller:inst|State.s3"
        Info: Encoded state bit "controller:inst|State.s2"
        Info: Encoded state bit "controller:inst|State.s1"
        Info: Encoded state bit "controller:inst|State.s0"
    Info: State "|jiaotongdeng|controller:inst|State.s0" uses code string "0000"
    Info: State "|jiaotongdeng|controller:inst|State.s1" uses code string "0011"
    Info: State "|jiaotongdeng|controller:inst|State.s2" uses code string "0101"
    Info: State "|jiaotongdeng|controller:inst|State.s3" uses code string "1001"
Info: Implemented 52 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 12 output pins
    Info: Implemented 37 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Apr 08 11:41:00 2008
    Info: Elapsed time: 00:00:04