jiaotongdeng.tan.rpt

来自「用VHDL做的交通灯设计」· RPT 代码 · 共 320 行 · 第 1/3 页

; N/A   ; None              ; 13.489 ns       ; Hold ; RA ;
; N/A   ; None              ; 13.484 ns       ; Hold ; RB ;
; N/A   ; None              ; 13.460 ns       ; Hold ; GA ;
; N/A   ; None              ; 13.450 ns       ; Hold ; YA ;
+-------+-------------------+-----------------+------+----+


+----------------------------------------------------------------------------------+
; th                                                                               ;
+---------------+-------------+-----------+------+----------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                   ; To Clock ;
+---------------+-------------+-----------+------+----------------------+----------+
; N/A           ; None        ; -7.591 ns ; Hold ; counter:inst1|Num[5] ; Clk      ;
; N/A           ; None        ; -7.596 ns ; Hold ; counter:inst1|Num[1] ; Clk      ;
; N/A           ; None        ; -7.597 ns ; Hold ; counter:inst1|Num[0] ; Clk      ;
; N/A           ; None        ; -7.774 ns ; Hold ; counter:inst1|Num[2] ; Clk      ;
; N/A           ; None        ; -8.015 ns ; Hold ; counter:inst1|Num[3] ; Clk      ;
; N/A           ; None        ; -8.021 ns ; Hold ; counter:inst1|Num[4] ; Clk      ;
+---------------+-------------+-----------+------+----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Tue Apr 08 11:41:11 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jiaotongdeng -c jiaotongdeng --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk" is an undefined clock
Info: Clock "Clk" has Internal fmax of 89.61 MHz between source register "counter:inst1|Num[1]" and destination register "controller:inst|State.s3" (period= 11.16 ns)
    Info: + Longest register to register delay is 5.319 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y18_N6; Fanout = 10; REG Node = 'counter:inst1|Num[1]'
        Info: 2: + IC(0.784 ns) + CELL(0.590 ns) = 1.374 ns; Loc. = LC_X5_Y18_N0; Fanout = 2; COMB Node = 'controller:inst|reduce_nor~59'
        Info: 3: + IC(0.437 ns) + CELL(0.114 ns) = 1.925 ns; Loc. = LC_X5_Y18_N1; Fanout = 3; COMB Node = 'controller:inst|reduce_nor~2'
        Info: 4: + IC(0.431 ns) + CELL(0.590 ns) = 2.946 ns; Loc. = LC_X5_Y18_N9; Fanout = 2; COMB Node = 'controller:inst|Select~502'
        Info: 5: + IC(0.445 ns) + CELL(0.590 ns) = 3.981 ns; Loc. = LC_X5_Y18_N2; Fanout = 2; COMB Node = 'controller:inst|Select~507'
        Info: 6: + IC(0.471 ns) + CELL(0.867 ns) = 5.319 ns; Loc. = LC_X5_Y18_N6; Fanout = 2; REG Node = 'controller:inst|State.s3'
        Info: Total cell delay = 2.751 ns ( 51.72 % )
        Info: Total interconnect delay = 2.568 ns ( 48.28 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "Clk" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X5_Y18_N6; Fanout = 2; REG Node = 'controller:inst|State.s3'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "Clk" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y18_N6; Fanout = 10; REG Node = 'counter:inst1|Num[1]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "counter:inst1|Num[4]" (data pin = "Hold", clock pin = "Clk") is 8.073 ns
    Info: + Longest pin to register delay is 10.990 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_175; Fanout = 7; PIN Node = 'Hold'
        Info: 2: + IC(7.685 ns) + CELL(0.590 ns) = 9.744 ns; Loc. = LC_X4_Y18_N1; Fanout = 6; COMB Node = 'counter:inst1|Num[5]~733'
        Info: 3: + IC(0.508 ns) + CELL(0.738 ns) = 10.990 ns; Loc. = LC_X4_Y18_N3; Fanout = 10; REG Node = 'counter:inst1|Num[4]'
        Info: Total cell delay = 2.797 ns ( 25.45 % )
        Info: Total interconnect delay = 8.193 ns ( 74.55 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "Clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y18_N3; Fanout = 10; REG Node = 'counter:inst1|Num[4]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "Clk" to destination pin "RB" through register "controller:inst|State.s1" is 9.204 ns
    Info: + Longest clock path from clock "Clk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X3_Y18_N7; Fanout = 5; REG Node = 'controller:inst|State.s1'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.026 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y18_N7; Fanout = 5; REG Node = 'controller:inst|State.s1'
        Info: 2: + IC(1.219 ns) + CELL(0.590 ns) = 1.809 ns; Loc. = LC_X6_Y18_N2; Fanout = 1; COMB Node = 'controller:inst|RB~3'
        Info: 3: + IC(2.093 ns) + CELL(2.124 ns) = 6.026 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'RB'
        Info: Total cell delay = 2.714 ns ( 45.04 % )
        Info: Total interconnect delay = 3.312 ns ( 54.96 % )
Info: Longest tpd from source pin "Hold" to destination pin "GB" is 13.522 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_175; Fanout = 7; PIN Node = 'Hold'
    Info: 2: + IC(7.513 ns) + CELL(0.292 ns) = 9.274 ns; Loc. = LC_X6_Y18_N4; Fanout = 1; COMB Node = 'controller:inst|GB~10'
    Info: 3: + IC(2.124 ns) + CELL(2.124 ns) = 13.522 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'GB'
    Info: Total cell delay = 3.885 ns ( 28.73 % )
    Info: Total interconnect delay = 9.637 ns ( 71.27 % )
Info: th for register "counter:inst1|Num[5]" (data pin = "Hold", clock pin = "Clk") is -7.591 ns
    Info: + Longest clock path from clock "Clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y18_N4; Fanout = 8; REG Node = 'counter:inst1|Num[5]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 10.560 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_175; Fanout = 7; PIN Node = 'Hold'
        Info: 2: + IC(7.685 ns) + CELL(0.590 ns) = 9.744 ns; Loc. = LC_X4_Y18_N1; Fanout = 6; COMB Node = 'counter:inst1|Num[5]~733'
        Info: 3: + IC(0.507 ns) + CELL(0.309 ns) = 10.560 ns; Loc. = LC_X4_Y18_N4; Fanout = 8; REG Node = 'counter:inst1|Num[5]'
        Info: Total cell delay = 2.368 ns ( 22.42 % )
        Info: Total interconnect delay = 8.192 ns ( 77.58 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Apr 08 11:41:12 2008
    Info: Elapsed time: 00:00:01