jiaotongdeng.map.qmsg

来自「用VHDL做的交通灯设计」· QMSG 代码 · 共 15 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 08 11:40:56 2008 " "Info: Processing started: Tue Apr 08 11:40:56 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter_architecture " "Info: Found design unit 1: counter-counter_architecture" {  } { { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 controller-controller_architecture " "Info: Found design unit 1: controller-controller_architecture" {  } { { "controller.vhd" "" { Text "E:/jiaotongdeng/controller.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 controller " "Info: Found entity 1: controller" {  } { { "controller.vhd" "" { Text "E:/jiaotongdeng/controller.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jiaotongdeng.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file jiaotongdeng.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 jiaotongdeng " "Info: Found entity 1: jiaotongdeng" {  } { { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jiaotongdeng " "Info: Elaborating entity \"jiaotongdeng\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "controller controller:inst " "Info: Elaborating entity \"controller\" for hierarchy \"controller:inst\"" {  } { { "jiaotongdeng.bdf" "inst" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 176 328 448 336 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst1 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst1\"" {  } { { "jiaotongdeng.bdf" "inst1" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 56 224 360 152 "inst1" "" } } } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|jiaotongdeng\|controller:inst\|State 4 0 " "Info: State machine \"\|jiaotongdeng\|controller:inst\|State\" contains 4 states and 0 state bits" {  } { { "controller.vhd" "" { Text "E:/jiaotongdeng/controller.vhd" 11 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|jiaotongdeng\|controller:inst\|State " "Info: Selected Auto state machine encoding method for state machine \"\|jiaotongdeng\|controller:inst\|State\"" {  } { { "controller.vhd" "" { Text "E:/jiaotongdeng/controller.vhd" 11 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|jiaotongdeng\|controller:inst\|State " "Info: Encoding result for state machine \"\|jiaotongdeng\|controller:inst\|State\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "controller:inst\|State.s3 " "Info: Encoded state bit \"controller:inst\|State.s3\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "controller:inst\|State.s2 " "Info: Encoded state bit \"controller:inst\|State.s2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "controller:inst\|State.s1 " "Info: Encoded state bit \"controller:inst\|State.s1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "controller:inst\|State.s0 " "Info: Encoded state bit \"controller:inst\|State.s0\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiaotongdeng\|controller:inst\|State.s0 0000 " "Info: State \"\|jiaotongdeng\|controller:inst\|State.s0\" uses code string \"0000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiaotongdeng\|controller:inst\|State.s1 0011 " "Info: State \"\|jiaotongdeng\|controller:inst\|State.s1\" uses code string \"0011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiaotongdeng\|controller:inst\|State.s2 0101 " "Info: State \"\|jiaotongdeng\|controller:inst\|State.s2\" uses code string \"0101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|jiaotongdeng\|controller:inst\|State.s3 1001 " "Info: State \"\|jiaotongdeng\|controller:inst\|State.s3\" uses code string \"1001\"" {  } {  } 0}  } { { "controller.vhd" "" { Text "E:/jiaotongdeng/controller.vhd" 11 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "52 " "Info: Implemented 52 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "37 " "Info: Implemented 37 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 08 11:41:00 2008 " "Info: Processing ended: Tue Apr 08 11:41:00 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}