jiaotongdeng.hier_info

用VHDL做的交通灯设计

|jiaotongdeng
GA <= controller:inst.GA
Hold => controller:inst.Hold
Hold => counter:inst1.Hold
Reset => controller:inst.Reset
Reset => counter:inst1.Reset
Clk => controller:inst.Clk
Clk => counter:inst1.Clk
GB <= controller:inst.GB
YA <= controller:inst.YA
YB <= controller:inst.YB
RA <= controller:inst.RA
RB <= controller:inst.RB
num[0] <= counter:inst1.Num[0]
num[1] <= counter:inst1.Num[1]
num[2] <= counter:inst1.Num[2]
num[3] <= counter:inst1.Num[3]
num[4] <= counter:inst1.Num[4]
num[5] <= counter:inst1.Num[5]


|jiaotongdeng|controller:inst
Hold => RA~1.OUTPUTSELECT
Hold => GA~0.OUTPUTSELECT
Hold => YA~0.OUTPUTSELECT
Hold => RB~0.OUTPUTSELECT
Hold => GB~0.OUTPUTSELECT
Hold => YB~0.OUTPUTSELECT
Reset => State~17.IN1
Clk => State~16.IN1
Num[0] => reduce_nor~0.IN3
Num[0] => reduce_nor~3.IN3
Num[0] => reduce_nor~1.IN3
Num[0] => reduce_nor~2.IN3
Num[1] => reduce_nor~0.IN2
Num[1] => reduce_nor~1.IN2
Num[1] => reduce_nor~2.IN2
Num[1] => reduce_nor~3.IN2
Num[2] => reduce_nor~1.IN4
Num[2] => reduce_nor~3.IN4
Num[2] => reduce_nor~0.IN4
Num[2] => reduce_nor~2.IN4
Num[3] => reduce_nor~0.IN1
Num[3] => reduce_nor~3.IN1
Num[3] => reduce_nor~1.IN1
Num[3] => reduce_nor~2.IN1
Num[4] => reduce_nor~2.IN5
Num[4] => reduce_nor~3.IN5
Num[4] => reduce_nor~0.IN5
Num[4] => reduce_nor~1.IN5
Num[5] => reduce_nor~0.IN0
Num[5] => reduce_nor~1.IN0
Num[5] => reduce_nor~3.IN0
Num[5] => reduce_nor~2.IN0
GA <= GA~0.DB_MAX_OUTPUT_PORT_TYPE
GB <= GB~0.DB_MAX_OUTPUT_PORT_TYPE
YA <= YA~0.DB_MAX_OUTPUT_PORT_TYPE
YB <= YB~0.DB_MAX_OUTPUT_PORT_TYPE
RA <= RA~1.DB_MAX_OUTPUT_PORT_TYPE
RB <= RB~0.DB_MAX_OUTPUT_PORT_TYPE


|jiaotongdeng|counter:inst1
Hold => Num[4]~reg0.ENA
Hold => Num[3]~reg0.ENA
Hold => Num[2]~reg0.ENA
Hold => Num[1]~reg0.ENA
Hold => Num[0]~reg0.ENA
Hold => Num[5]~reg0.ENA
Reset => Num[4]~reg0.ACLR
Reset => Num[3]~reg0.ACLR
Reset => Num[2]~reg0.ACLR
Reset => Num[1]~reg0.ACLR
Reset => Num[0]~reg0.ACLR
Reset => Num[5]~reg0.ACLR
Clk => Num[4]~reg0.CLK
Clk => Num[3]~reg0.CLK
Clk => Num[2]~reg0.CLK
Clk => Num[1]~reg0.CLK
Clk => Num[0]~reg0.CLK
Clk => Num[5]~reg0.CLK
Num[0] <= Num[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Num[1] <= Num[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Num[2] <= Num[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Num[3] <= Num[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Num[4] <= Num[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Num[5] <= Num[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE