jiaotongdeng.tan.qmsg

用VHDL做的交通灯设计

{ "Info" "ITDB_TH_RESULT" "counter:inst1\|Num\[5\] Hold Clk -7.591 ns register " "Info: th for register \"counter:inst1\|Num\[5\]\" (data pin = \"Hold\", clock pin = \"Clk\") is -7.591 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_28 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { Clk } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 144 0 168 160 "Clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns counter:inst1\|Num\[5\] 2 REG LC_X4_Y18_N4 8 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y18_N4; Fanout = 8; REG Node = 'counter:inst1\|Num\[5\]'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.485 ns" { Clk counter:inst1|Num[5] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk counter:inst1|Num[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 counter:inst1|Num[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.560 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Hold 1 PIN PIN_175 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_175; Fanout = 7; PIN Node = 'Hold'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { Hold } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 48 0 168 64 "Hold" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.685 ns) + CELL(0.590 ns) 9.744 ns counter:inst1\|Num\[5\]~733 2 COMB LC_X4_Y18_N1 6 " "Info: 2: + IC(7.685 ns) + CELL(0.590 ns) = 9.744 ns; Loc. = LC_X4_Y18_N1; Fanout = 6; COMB Node = 'counter:inst1\|Num\[5\]~733'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "8.275 ns" { Hold counter:inst1|Num[5]~733 } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.507 ns) + CELL(0.309 ns) 10.560 ns counter:inst1\|Num\[5\] 3 REG LC_X4_Y18_N4 8 " "Info: 3: + IC(0.507 ns) + CELL(0.309 ns) = 10.560 ns; Loc. = LC_X4_Y18_N4; Fanout = 8; REG Node = 'counter:inst1\|Num\[5\]'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "0.816 ns" { counter:inst1|Num[5]~733 counter:inst1|Num[5] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.368 ns 22.42 % " "Info: Total cell delay = 2.368 ns ( 22.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.192 ns 77.58 % " "Info: Total interconnect delay = 8.192 ns ( 77.58 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "10.560 ns" { Hold counter:inst1|Num[5]~733 counter:inst1|Num[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.560 ns" { Hold Hold~out0 counter:inst1|Num[5]~733 counter:inst1|Num[5] } { 0.000ns 0.000ns 7.685ns 0.507ns } { 0.000ns 1.469ns 0.590ns 0.309ns } } }  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk counter:inst1|Num[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 counter:inst1|Num[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "10.560 ns" { Hold counter:inst1|Num[5]~733 counter:inst1|Num[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.560 ns" { Hold Hold~out0 counter:inst1|Num[5]~733 counter:inst1|Num[5] } { 0.000ns 0.000ns 7.685ns 0.507ns } { 0.000ns 1.469ns 0.590ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 08 11:41:12 2008 " "Info: Processing ended: Tue Apr 08 11:41:12 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}