jiaotongdeng.tan.qmsg

用VHDL做的交通灯设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register counter:inst1\|Num\[1\] register controller:inst\|State.s3 89.61 MHz 11.16 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 89.61 MHz between source register \"counter:inst1\|Num\[1\]\" and destination register \"controller:inst\|State.s3\" (period= 11.16 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.319 ns + Longest register register " "Info: + Longest register to register delay is 5.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst1\|Num\[1\] 1 REG LC_X4_Y18_N6 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y18_N6; Fanout = 10; REG Node = 'counter:inst1\|Num\[1\]'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { counter:inst1|Num[1] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.590 ns) 1.374 ns controller:inst\|reduce_nor~59 2 COMB LC_X5_Y18_N0 2 " "Info: 2: + IC(0.784 ns) + CELL(0.590 ns) = 1.374 ns; Loc. = LC_X5_Y18_N0; Fanout = 2; COMB Node = 'controller:inst\|reduce_nor~59'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.374 ns" { counter:inst1|Num[1] controller:inst|reduce_nor~59 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.114 ns) 1.925 ns controller:inst\|reduce_nor~2 3 COMB LC_X5_Y18_N1 3 " "Info: 3: + IC(0.437 ns) + CELL(0.114 ns) = 1.925 ns; Loc. = LC_X5_Y18_N1; Fanout = 3; COMB Node = 'controller:inst\|reduce_nor~2'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "0.551 ns" { controller:inst|reduce_nor~59 controller:inst|reduce_nor~2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.590 ns) 2.946 ns controller:inst\|Select~502 4 COMB LC_X5_Y18_N9 2 " "Info: 4: + IC(0.431 ns) + CELL(0.590 ns) = 2.946 ns; Loc. = LC_X5_Y18_N9; Fanout = 2; COMB Node = 'controller:inst\|Select~502'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.021 ns" { controller:inst|reduce_nor~2 controller:inst|Select~502 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.590 ns) 3.981 ns controller:inst\|Select~507 5 COMB LC_X5_Y18_N2 2 " "Info: 5: + IC(0.445 ns) + CELL(0.590 ns) = 3.981 ns; Loc. = LC_X5_Y18_N2; Fanout = 2; COMB Node = 'controller:inst\|Select~507'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.035 ns" { controller:inst|Select~502 controller:inst|Select~507 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.471 ns) + CELL(0.867 ns) 5.319 ns controller:inst\|State.s3 6 REG LC_X5_Y18_N6 2 " "Info: 6: + IC(0.471 ns) + CELL(0.867 ns) = 5.319 ns; Loc. = LC_X5_Y18_N6; Fanout = 2; REG Node = 'controller:inst\|State.s3'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.338 ns" { controller:inst|Select~507 controller:inst|State.s3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.751 ns 51.72 % " "Info: Total cell delay = 2.751 ns ( 51.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.568 ns 48.28 % " "Info: Total interconnect delay = 2.568 ns ( 48.28 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "5.319 ns" { counter:inst1|Num[1] controller:inst|reduce_nor~59 controller:inst|reduce_nor~2 controller:inst|Select~502 controller:inst|Select~507 controller:inst|State.s3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.319 ns" { counter:inst1|Num[1] controller:inst|reduce_nor~59 controller:inst|reduce_nor~2 controller:inst|Select~502 controller:inst|Select~507 controller:inst|State.s3 } { 0.000ns 0.784ns 0.437ns 0.431ns 0.445ns 0.471ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_28 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { Clk } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 144 0 168 160 "Clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns controller:inst\|State.s3 2 REG LC_X5_Y18_N6 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X5_Y18_N6; Fanout = 2; REG Node = 'controller:inst\|State.s3'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.485 ns" { Clk controller:inst|State.s3 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk controller:inst|State.s3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 controller:inst|State.s3 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_28 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { Clk } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 144 0 168 160 "Clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns counter:inst1\|Num\[1\] 2 REG LC_X4_Y18_N6 10 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y18_N6; Fanout = 10; REG Node = 'counter:inst1\|Num\[1\]'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.485 ns" { Clk counter:inst1|Num[1] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk counter:inst1|Num[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 counter:inst1|Num[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk controller:inst|State.s3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 controller:inst|State.s3 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk counter:inst1|Num[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 counter:inst1|Num[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "5.319 ns" { counter:inst1|Num[1] controller:inst|reduce_nor~59 controller:inst|reduce_nor~2 controller:inst|Select~502 controller:inst|Select~507 controller:inst|State.s3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.319 ns" { counter:inst1|Num[1] controller:inst|reduce_nor~59 controller:inst|reduce_nor~2 controller:inst|Select~502 controller:inst|Select~507 controller:inst|State.s3 } { 0.000ns 0.784ns 0.437ns 0.431ns 0.445ns 0.471ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.590ns 0.867ns } } } { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk controller:inst|State.s3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 controller:inst|State.s3 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk counter:inst1|Num[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 counter:inst1|Num[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "counter:inst1\|Num\[4\] Hold Clk 8.073 ns register " "Info: tsu for register \"counter:inst1\|Num\[4\]\" (data pin = \"Hold\", clock pin = \"Clk\") is 8.073 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.990 ns + Longest pin register " "Info: + Longest pin to register delay is 10.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Hold 1 PIN PIN_175 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_175; Fanout = 7; PIN Node = 'Hold'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { Hold } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 48 0 168 64 "Hold" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.685 ns) + CELL(0.590 ns) 9.744 ns counter:inst1\|Num\[5\]~733 2 COMB LC_X4_Y18_N1 6 " "Info: 2: + IC(7.685 ns) + CELL(0.590 ns) = 9.744 ns; Loc. = LC_X4_Y18_N1; Fanout = 6; COMB Node = 'counter:inst1\|Num\[5\]~733'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "8.275 ns" { Hold counter:inst1|Num[5]~733 } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.508 ns) + CELL(0.738 ns) 10.990 ns counter:inst1\|Num\[4\] 3 REG LC_X4_Y18_N3 10 " "Info: 3: + IC(0.508 ns) + CELL(0.738 ns) = 10.990 ns; Loc. = LC_X4_Y18_N3; Fanout = 10; REG Node = 'counter:inst1\|Num\[4\]'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.246 ns" { counter:inst1|Num[5]~733 counter:inst1|Num[4] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.797 ns 25.45 % " "Info: Total cell delay = 2.797 ns ( 25.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.193 ns 74.55 % " "Info: Total interconnect delay = 8.193 ns ( 74.55 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "10.990 ns" { Hold counter:inst1|Num[5]~733 counter:inst1|Num[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.990 ns" { Hold Hold~out0 counter:inst1|Num[5]~733 counter:inst1|Num[4] } { 0.000ns 0.000ns 7.685ns 0.508ns } { 0.000ns 1.469ns 0.590ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_28 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { Clk } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 144 0 168 160 "Clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns counter:inst1\|Num\[4\] 2 REG LC_X4_Y18_N3 10 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y18_N3; Fanout = 10; REG Node = 'counter:inst1\|Num\[4\]'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.485 ns" { Clk counter:inst1|Num[4] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk counter:inst1|Num[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 counter:inst1|Num[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "10.990 ns" { Hold counter:inst1|Num[5]~733 counter:inst1|Num[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.990 ns" { Hold Hold~out0 counter:inst1|Num[5]~733 counter:inst1|Num[4] } { 0.000ns 0.000ns 7.685ns 0.508ns } { 0.000ns 1.469ns 0.590ns 0.738ns } } } { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk counter:inst1|Num[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 counter:inst1|Num[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk RB controller:inst\|State.s1 9.204 ns register " "Info: tco from clock \"Clk\" to destination pin \"RB\" through register \"controller:inst\|State.s1\" is 9.204 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clk 1 CLK PIN_28 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; CLK Node = 'Clk'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { Clk } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 144 0 168 160 "Clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns controller:inst\|State.s1 2 REG LC_X3_Y18_N7 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X3_Y18_N7; Fanout = 5; REG Node = 'controller:inst\|State.s1'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.485 ns" { Clk controller:inst|State.s1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk controller:inst|State.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 controller:inst|State.s1 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.026 ns + Longest register pin " "Info: + Longest register to pin delay is 6.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns controller:inst\|State.s1 1 REG LC_X3_Y18_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y18_N7; Fanout = 5; REG Node = 'controller:inst\|State.s1'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { controller:inst|State.s1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.219 ns) + CELL(0.590 ns) 1.809 ns controller:inst\|RB~3 2 COMB LC_X6_Y18_N2 1 " "Info: 2: + IC(1.219 ns) + CELL(0.590 ns) = 1.809 ns; Loc. = LC_X6_Y18_N2; Fanout = 1; COMB Node = 'controller:inst\|RB~3'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.809 ns" { controller:inst|State.s1 controller:inst|RB~3 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/jiaotongdeng/controller.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.093 ns) + CELL(2.124 ns) 6.026 ns RB 3 PIN PIN_12 0 " "Info: 3: + IC(2.093 ns) + CELL(2.124 ns) = 6.026 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'RB'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "4.217 ns" { controller:inst|RB~3 RB } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 280 568 744 296 "RB" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns 45.04 % " "Info: Total cell delay = 2.714 ns ( 45.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.312 ns 54.96 % " "Info: Total interconnect delay = 3.312 ns ( 54.96 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "6.026 ns" { controller:inst|State.s1 controller:inst|RB~3 RB } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.026 ns" { controller:inst|State.s1 controller:inst|RB~3 RB } { 0.000ns 1.219ns 2.093ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "2.954 ns" { Clk controller:inst|State.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { Clk Clk~out0 controller:inst|State.s1 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "6.026 ns" { controller:inst|State.s1 controller:inst|RB~3 RB } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.026 ns" { controller:inst|State.s1 controller:inst|RB~3 RB } { 0.000ns 1.219ns 2.093ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Hold GB 13.522 ns Longest " "Info: Longest tpd from source pin \"Hold\" to destination pin \"GB\" is 13.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Hold 1 PIN PIN_175 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_175; Fanout = 7; PIN Node = 'Hold'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { Hold } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 48 0 168 64 "Hold" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.513 ns) + CELL(0.292 ns) 9.274 ns controller:inst\|GB~10 2 COMB LC_X6_Y18_N4 1 " "Info: 2: + IC(7.513 ns) + CELL(0.292 ns) = 9.274 ns; Loc. = LC_X6_Y18_N4; Fanout = 1; COMB Node = 'controller:inst\|GB~10'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "7.805 ns" { Hold controller:inst|GB~10 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/jiaotongdeng/controller.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.124 ns) + CELL(2.124 ns) 13.522 ns GB 3 PIN PIN_14 0 " "Info: 3: + IC(2.124 ns) + CELL(2.124 ns) = 13.522 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'GB'" {  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "4.248 ns" { controller:inst|GB~10 GB } "NODE_NAME" } "" } } { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 216 568 744 232 "GB" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.885 ns 28.73 % " "Info: Total cell delay = 3.885 ns ( 28.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.637 ns 71.27 % " "Info: Total interconnect delay = 9.637 ns ( 71.27 % )" {  } {  } 0}  } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "13.522 ns" { Hold controller:inst|GB~10 GB } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.522 ns" { Hold Hold~out0 controller:inst|GB~10 GB } { 0.000ns 0.000ns 7.513ns 2.124ns } { 0.000ns 1.469ns 0.292ns 2.124ns } } }  } 0}