jiaotongdeng.tan.qmsg

来自「用VHDL做的交通灯设计」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 08 11:41:11 2008 " "Info: Processing started: Tue Apr 08 11:41:11 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off jiaotongdeng -c jiaotongdeng --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jiaotongdeng -c jiaotongdeng --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" {  } { { "jiaotongdeng.bdf" "" { Schematic "E:/jiaotongdeng/jiaotongdeng.bdf" { { 144 0 168 160 "Clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0}  } {  } 0}