jiaotongdeng.fit.qmsg
来自「用VHDL做的交通灯设计」· QMSG 代码 · 共 41 行 · 第 1/2 页
QMSG
41 行
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" { } { } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 3.30 0 6 0 " "Info: Number of I/O pins in group: 6 (unused VREF, 3.30 VCCIO, 0 input, 6 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." { } { } 0} } { } 0} } { } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 9 35 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 9 total pin(s) used -- 35 pins available" { } { } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 2 43 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 43 pins available" { } { } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0} } { } 0} } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.261 ns register register " "Info: Estimated most critical path is register to register delay of 4.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst1\|Num\[3\] 1 REG LAB_X4_Y18 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y18; Fanout = 9; REG Node = 'counter:inst1\|Num\[3\]'" { } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "" { counter:inst1|Num[3] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "E:/jiaotongdeng/counter.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.590 ns) 0.966 ns controller:inst\|reduce_nor~59 2 COMB LAB_X5_Y18 2 " "Info: 2: + IC(0.376 ns) + CELL(0.590 ns) = 0.966 ns; Loc. = LAB_X5_Y18; Fanout = 2; COMB Node = 'controller:inst\|reduce_nor~59'" { } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "0.966 ns" { counter:inst1|Num[3] controller:inst|reduce_nor~59 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.114 ns) 1.630 ns controller:inst\|reduce_nor~2 3 COMB LAB_X5_Y18 3 " "Info: 3: + IC(0.550 ns) + CELL(0.114 ns) = 1.630 ns; Loc. = LAB_X5_Y18; Fanout = 3; COMB Node = 'controller:inst\|reduce_nor~2'" { } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "0.664 ns" { controller:inst|reduce_nor~59 controller:inst|reduce_nor~2 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 2.294 ns controller:inst\|Select~502 4 COMB LAB_X5_Y18 2 " "Info: 4: + IC(0.074 ns) + CELL(0.590 ns) = 2.294 ns; Loc. = LAB_X5_Y18; Fanout = 2; COMB Node = 'controller:inst\|Select~502'" { } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "0.664 ns" { controller:inst|reduce_nor~2 controller:inst|Select~502 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.442 ns) 2.958 ns controller:inst\|Select~507 5 COMB LAB_X5_Y18 2 " "Info: 5: + IC(0.222 ns) + CELL(0.442 ns) = 2.958 ns; Loc. = LAB_X5_Y18; Fanout = 2; COMB Node = 'controller:inst\|Select~507'" { } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "0.664 ns" { controller:inst|Select~502 controller:inst|Select~507 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.867 ns) 4.261 ns controller:inst\|State.s0 6 REG LAB_X5_Y18 4 " "Info: 6: + IC(0.436 ns) + CELL(0.867 ns) = 4.261 ns; Loc. = LAB_X5_Y18; Fanout = 4; REG Node = 'controller:inst\|State.s0'" { } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "1.303 ns" { controller:inst|Select~507 controller:inst|State.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.603 ns 61.09 % " "Info: Total cell delay = 2.603 ns ( 61.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.658 ns 38.91 % " "Info: Total interconnect delay = 1.658 ns ( 38.91 % )" { } { } 0} } { { "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" "" { Report "E:/jiaotongdeng/db/jiaotongdeng_cmp.qrpt" Compiler "jiaotongdeng" "UNKNOWN" "V1" "E:/jiaotongdeng/db/jiaotongdeng.quartus_db" { Floorplan "E:/jiaotongdeng/" "" "4.261 ns" { counter:inst1|Num[3] controller:inst|reduce_nor~59 controller:inst|reduce_nor~2 controller:inst|Select~502 controller:inst|Select~507 controller:inst|State.s0 } "NODE_NAME" } "" } } } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { } { } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" { } { } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 08 11:41:06 2008 " "Info: Processing ended: Tue Apr 08 11:41:06 2008" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0} } { } 0}
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