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📄 jiaotongdeng.vho

📁 用VHDL做的交通灯设计
💻 VHO
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1234 
-- pragma translate_on
PORT MAP (
	pathsel => inst_areduce_nor_a59_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a1_a,
	datab => inst1_aNum_a3_a,
	datac => inst1_aNum_a0_a,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_areduce_nor_a59_I_modesel,
	combout => inst_areduce_nor_a59);

inst_areduce_nor_a2_I : cyclone_lcell
-- Equation(s):
-- inst_areduce_nor_a2 = inst1_aNum_a4_a # !inst_areduce_nor_a59 # !inst1_aNum_a2_a # !inst1_aNum_a5_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "BFFF",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_areduce_nor_a2_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a4_a,
	datab => inst1_aNum_a5_a,
	datac => inst1_aNum_a2_a,
	datad => inst_areduce_nor_a59,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_areduce_nor_a2_I_modesel,
	combout => inst_areduce_nor_a2);

inst_areduce_nor_a60_I : cyclone_lcell
-- Equation(s):
-- inst_areduce_nor_a60 = inst1_aNum_a1_a # inst1_aNum_a2_a # !inst1_aNum_a3_a # !inst1_aNum_a0_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "FFBF",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_areduce_nor_a60_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a1_a,
	datab => inst1_aNum_a0_a,
	datac => inst1_aNum_a3_a,
	datad => inst1_aNum_a2_a,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_areduce_nor_a60_I_modesel,
	combout => inst_areduce_nor_a60);

inst_aSelect_a503_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a503 = !inst1_aNum_a5_a & inst1_aNum_a4_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0F00",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a503_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => VCC,
	datac => inst1_aNum_a5_a,
	datad => inst1_aNum_a4_a,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a503_I_modesel,
	combout => inst_aSelect_a503);

inst_aSelect_a505_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a505 = !inst1_aNum_a1_a & !inst1_aNum_a0_a & (!inst1_aNum_a3_a)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0011",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a505_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a1_a,
	datab => inst1_aNum_a0_a,
	datac => VCC,
	datad => inst1_aNum_a3_a,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a505_I_modesel,
	combout => inst_aSelect_a505);

inst_aSelect_a506_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a506 = inst1_aNum_a2_a & inst_aSelect_a503 & !inst_aState_as0 & inst_aSelect_a505

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0800",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a506_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a2_a,
	datab => inst_aSelect_a503,
	datac => inst_aState_as0,
	datad => inst_aSelect_a505,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a506_I_modesel,
	combout => inst_aSelect_a506);

inst_aSelect_a509_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a509 = inst_aState_as1 & (inst_areduce_nor_a60 # !inst_aSelect_a503) # !inst_aState_as1 & (inst_aSelect_a506)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "ACFC",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a509_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst_areduce_nor_a60,
	datab => inst_aSelect_a506,
	datac => inst_aState_as1,
	datad => inst_aSelect_a503,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a509_I_modesel,
	combout => inst_aSelect_a509);

inst_aState_as1_aI : cyclone_lcell
-- Equation(s):
-- inst_aState_as1 = DFFEAS(!inst_aSelect_a501 & inst_aSelect_a509 & (inst_areduce_nor_a2 # !inst_aState_as2), !GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "3100",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aState_as1_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => ALT_INV_Clk_acombout,
	dataa => inst_aState_as2,
	datab => inst_aSelect_a501,
	datac => inst_areduce_nor_a2,
	datad => inst_aSelect_a509,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aState_as1_aI_modesel,
	regout => inst_aState_as1);

inst_aSelect_a504_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a504 = inst1_aNum_a2_a # !inst_aSelect_a503 # !inst_aState_as1 # !inst_areduce_nor_a59

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "BFFF",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a504_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a2_a,
	datab => inst_areduce_nor_a59,
	datac => inst_aState_as1,
	datad => inst_aSelect_a503,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a504_I_modesel,
	combout => inst_aSelect_a504);

inst_aState_as2_aI : cyclone_lcell
-- Equation(s):
-- inst_aState_as2 = DFFEAS(!inst_aSelect_a501 & (inst_aState_as2 & (inst_areduce_nor_a2) # !inst_aState_as2 & !inst_aSelect_a504), !GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "3101",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aState_as2_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => ALT_INV_Clk_acombout,
	dataa => inst_aSelect_a504,
	datab => inst_aSelect_a501,
	datac => inst_aState_as2,
	datad => inst_areduce_nor_a2,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aState_as2_aI_modesel,
	regout => inst_aState_as2);

inst_aSelect_a502_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a502 = inst_areduce_nor_a2 # !inst_aState_as2

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "AAFF",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a502_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst_areduce_nor_a2,
	datab => VCC,
	datac => VCC,
	datad => inst_aState_as2,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a502_I_modesel,
	combout => inst_aSelect_a502);

inst_aSelect_a507_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a507 = inst_aSelect_a502 $ inst_aSelect_a504 $ inst_aSelect_a506 $ inst_aSelect_a501

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "6996",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a507_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst_aSelect_a502,
	datab => inst_aSelect_a504,
	datac => inst_aSelect_a506,
	datad => inst_aSelect_a501,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a507_I_modesel,
	combout => inst_aSelect_a507);

inst_aState_as3_aI : cyclone_lcell
-- Equation(s):
-- inst_aState_as3 = DFFEAS(!inst_aSelect_a502, !GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , inst_aSelect_a507, , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0F0F",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aState_as3_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => ALT_INV_Clk_acombout,
	dataa => VCC,
	datab => VCC,
	datac => inst_aSelect_a502,
	datad => VCC,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => inst_aSelect_a507,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aState_as3_aI_modesel,
	regout => inst_aState_as3);

inst_aSelect_a501_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a501 = inst_aState_as3 & !inst1_aNum_a5_a & !inst1_aNum_a4_a & inst_aSelect_a500

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0200",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a501_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst_aState_as3,
	datab => inst1_aNum_a5_a,
	datac => inst1_aNum_a4_a,
	datad => inst_aSelect_a500,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a501_I_modesel,
	combout => inst_aSelect_a501);

inst_aState_as0_aI : cyclone_lcell
-- Equation(s):
-- inst_aState_as0 = DFFEAS(!inst_aSelect_a501, !GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , inst_aSelect_a507, , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "00FF",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aState_as0_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => ALT_INV_Clk_acombout,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => inst_aSelect_a501,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => inst_aSelect_a507,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aState_as0_aI_modesel,
	regout => inst_aState_as0);

inst_aGA_a3_I : cyclone_lcell
-- Equation(s):
-- inst_aGA_a3 = Hold_acombout # inst_aState_as0

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "FFF0",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aGA_a3_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => VCC,
	datac => Hold_acombout,
	datad => inst_aState_as0,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
1234

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