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📄 jiaotongdeng.vho

📁 用VHDL做的交通灯设计
💻 VHO
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1234 
	datac => inst1_aLessThan_a56,
	datad => inst1_aNum_a5_a_a733,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aNum_a0_a_aI_modesel,
	regout => inst1_aNum_a0_a);

inst1_aadd_a144_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a144 = inst1_aNum_a1_a $ (inst1_aadd_a151)
-- inst1_aadd_a146 = CARRY(!inst1_aadd_a151 # !inst1_aNum_a1_a)
-- inst1_aadd_a146COUT1_156 = CARRY(!inst1_aadd_a151COUT1_155 # !inst1_aNum_a1_a)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "5A5F",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aadd_a144_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a1_a,
	datab => VCC,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => inst1_aadd_a151,
	cin1 => inst1_aadd_a151COUT1_155,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aadd_a144_I_modesel,
	combout => inst1_aadd_a144,
	cout0 => inst1_aadd_a146,
	cout1 => inst1_aadd_a146COUT1_156);

inst1_aNum_a1_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a1_a = DFFEAS(inst1_aNum_a5_a_a733 & inst1_aNum_a1_a # !inst1_aNum_a5_a_a733 & (inst1_aadd_a144 & inst1_aLessThan_a56), GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "AAC0",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aNum_a1_a_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => Clk_acombout,
	dataa => inst1_aNum_a1_a,
	datab => inst1_aadd_a144,
	datac => inst1_aLessThan_a56,
	datad => inst1_aNum_a5_a_a733,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aNum_a1_a_aI_modesel,
	regout => inst1_aNum_a1_a);

inst_aSelect_a500_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a500 = !inst1_aNum_a2_a & !inst1_aNum_a0_a & !inst1_aNum_a3_a & !inst1_aNum_a1_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "0001",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst_aSelect_a500_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a2_a,
	datab => inst1_aNum_a0_a,
	datac => inst1_aNum_a3_a,
	datad => inst1_aNum_a1_a,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst_aSelect_a500_I_modesel,
	combout => inst_aSelect_a500);

inst1_aLessThan_a56_I : cyclone_lcell
-- Equation(s):
-- inst1_aLessThan_a56 = inst_aSelect_a500 # !inst1_aNum_a4_a # !inst1_aNum_a5_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "CFFF",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aLessThan_a56_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => inst_aSelect_a500,
	datac => inst1_aNum_a5_a,
	datad => inst1_aNum_a4_a,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aLessThan_a56_I_modesel,
	combout => inst1_aLessThan_a56);

inst1_aadd_a139_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a139 = inst1_aNum_a2_a $ !inst1_aadd_a146
-- inst1_aadd_a141 = CARRY(inst1_aNum_a2_a & !inst1_aadd_a146)
-- inst1_aadd_a141COUT1 = CARRY(inst1_aNum_a2_a & !inst1_aadd_a146COUT1_156)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "C30C",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aadd_a139_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => inst1_aNum_a2_a,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => inst1_aadd_a146,
	cin1 => inst1_aadd_a146COUT1_156,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aadd_a139_I_modesel,
	combout => inst1_aadd_a139,
	cout0 => inst1_aadd_a141,
	cout1 => inst1_aadd_a141COUT1);

inst1_aNum_a2_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a2_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a2_a) # !inst1_aNum_a5_a_a733 & inst1_aLessThan_a56 & inst1_aadd_a139, GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "F088",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aNum_a2_a_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => Clk_acombout,
	dataa => inst1_aLessThan_a56,
	datab => inst1_aadd_a139,
	datac => inst1_aNum_a2_a,
	datad => inst1_aNum_a5_a_a733,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aNum_a2_a_aI_modesel,
	regout => inst1_aNum_a2_a);

inst1_aadd_a134_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a134 = inst1_aNum_a3_a $ inst1_aadd_a141
-- inst1_aadd_a136 = 

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "3C3F",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aadd_a134_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => inst1_aNum_a3_a,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => inst1_aadd_a141,
	cin1 => inst1_aadd_a141COUT1,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aadd_a134_I_modesel,
	combout => inst1_aadd_a134,
	cout => inst1_aadd_a136);

inst1_aNum_a3_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a3_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a3_a) # !inst1_aNum_a5_a_a733 & inst1_aadd_a134 & inst1_aLessThan_a56, GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "EA40",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aNum_a3_a_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => Clk_acombout,
	dataa => inst1_aNum_a5_a_a733,
	datab => inst1_aadd_a134,
	datac => inst1_aLessThan_a56,
	datad => inst1_aNum_a3_a,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aNum_a3_a_aI_modesel,
	regout => inst1_aNum_a3_a);

inst1_aadd_a129_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a129 = inst1_aNum_a4_a $ (!(!inst1_aadd_a136 & GND) # (inst1_aadd_a136 & VCC))
-- inst1_aadd_a131 = CARRY(inst1_aNum_a4_a & (!inst1_aadd_a136))
-- inst1_aadd_a131COUT1_157 = CARRY(inst1_aNum_a4_a & (!inst1_aadd_a136))

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "A50A",
--	cin_used => "true",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aadd_a129_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a4_a,
	datab => VCC,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => inst1_aadd_a136,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aadd_a129_I_modesel,
	combout => inst1_aadd_a129,
	cout0 => inst1_aadd_a131,
	cout1 => inst1_aadd_a131COUT1_157);

inst1_aadd_a124_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a124 = (!inst1_aadd_a136 & inst1_aadd_a131) # (inst1_aadd_a136 & inst1_aadd_a131COUT1_157) $ inst1_aNum_a5_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "0FF0",
--	cin_used => "true",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aadd_a124_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => inst1_aNum_a5_a,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => inst1_aadd_a136,
	cin0 => inst1_aadd_a131,
	cin1 => inst1_aadd_a131COUT1_157,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aadd_a124_I_modesel,
	combout => inst1_aadd_a124);

inst1_aNum_a5_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a5_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a5_a) # !inst1_aNum_a5_a_a733 & inst1_aadd_a124 & inst1_aLessThan_a56, GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "F088",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aNum_a5_a_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => Clk_acombout,
	dataa => inst1_aadd_a124,
	datab => inst1_aLessThan_a56,
	datac => inst1_aNum_a5_a,
	datad => inst1_aNum_a5_a_a733,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aNum_a5_a_aI_modesel,
	regout => inst1_aNum_a5_a);

inst1_aNum_a5_a_a718_I : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a5_a_a718 = inst1_aNum_a1_a # inst1_aNum_a2_a # inst1_aNum_a3_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "FFFA",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aNum_a5_a_a718_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => inst1_aNum_a1_a,
	datab => VCC,
	datac => inst1_aNum_a2_a,
	datad => inst1_aNum_a3_a,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aNum_a5_a_a718_I_modesel,
	combout => inst1_aNum_a5_a_a718);

inst1_aNum_a5_a_a733_I : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a5_a_a733 = Hold_acombout # inst1_aNum_a5_a & inst1_aNum_a5_a_a718 & inst1_aNum_a4_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "EAAA",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aNum_a5_a_a733_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => Hold_acombout,
	datab => inst1_aNum_a5_a,
	datac => inst1_aNum_a5_a_a718,
	datad => inst1_aNum_a4_a,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aNum_a5_a_a733_I_modesel,
	combout => inst1_aNum_a5_a_a733);

inst1_aNum_a4_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a4_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a4_a) # !inst1_aNum_a5_a_a733 & inst1_aLessThan_a56 & inst1_aadd_a129, GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "EA40",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aNum_a4_a_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => Clk_acombout,
	dataa => inst1_aNum_a5_a_a733,
	datab => inst1_aLessThan_a56,
	datac => inst1_aadd_a129,
	datad => inst1_aNum_a4_a,
	aclr => Reset_acombout,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aNum_a4_a_aI_modesel,
	regout => inst1_aNum_a4_a);

inst_areduce_nor_a59_I : cyclone_lcell
-- Equation(s):
-- inst_areduce_nor_a59 = !inst1_aNum_a1_a & inst1_aNum_a3_a & inst1_aNum_a0_a

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "4040",
--	output_mode => "comb_only")
1234

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