jiaotongdeng.vho

用VHDL做的交通灯设计

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

-- DATE "04/08/2008 11:41:14"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	jiaotongdeng IS
    PORT (
	Hold : IN std_logic;
	Clk : IN std_logic;
	Reset : IN std_logic;
	GA : OUT std_logic;
	GB : OUT std_logic;
	YA : OUT std_logic;
	YB : OUT std_logic;
	RA : OUT std_logic;
	RB : OUT std_logic;
	num : OUT std_logic_vector(5 DOWNTO 0)
	);
END jiaotongdeng;

ARCHITECTURE structure OF jiaotongdeng IS
SIGNAL GNDs : std_logic_vector(255 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(255 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_Hold : std_logic;
SIGNAL ww_Clk : std_logic;
SIGNAL ww_Reset : std_logic;
SIGNAL ww_GA : std_logic;
SIGNAL ww_GB : std_logic;
SIGNAL ww_YA : std_logic;
SIGNAL ww_YB : std_logic;
SIGNAL ww_RA : std_logic;
SIGNAL ww_RB : std_logic;
SIGNAL ww_num : std_logic_vector(5 DOWNTO 0);
SIGNAL Clk_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL Hold_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL inst1_aadd_a149_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aadd_a149_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL Reset_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL inst1_aNum_a0_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aNum_a0_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aadd_a144_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aadd_a144_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aNum_a1_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aNum_a1_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a500_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a500_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aLessThan_a56_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aLessThan_a56_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aadd_a139_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aadd_a139_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aNum_a2_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aNum_a2_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aadd_a134_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aadd_a134_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aNum_a3_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aNum_a3_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aadd_a129_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aadd_a129_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aadd_a124_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aadd_a124_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aNum_a5_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aNum_a5_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aNum_a5_a_a718_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aNum_a5_a_a718_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aNum_a5_a_a733_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aNum_a5_a_a733_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst1_aNum_a4_a_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst1_aNum_a4_a_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_areduce_nor_a59_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_areduce_nor_a59_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_areduce_nor_a2_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_areduce_nor_a2_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_areduce_nor_a60_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_areduce_nor_a60_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a503_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a503_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a505_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a505_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a506_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a506_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a509_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a509_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aState_as1_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aState_as1_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a504_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a504_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aState_as2_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aState_as2_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a502_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a502_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a507_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a507_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aState_as3_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aState_as3_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aSelect_a501_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aSelect_a501_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aState_as0_aI_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aState_as0_aI_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aGA_a3_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aGA_a3_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aGB_a10_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aGB_a10_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aYA_a10_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aYA_a10_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aYB_a10_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aYB_a10_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aRA_a13_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aRA_a13_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL inst_aRB_a3_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL inst_aRB_a3_I_pathsel : std_logic_vector(10 DOWNTO 0);
SIGNAL GA_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL GB_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL YA_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL YB_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL RA_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL RB_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL num_a5_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL num_a4_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL num_a3_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL num_a2_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL num_a1_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL num_a0_a_aI_modesel : std_logic_vector(26 DOWNTO 0);
SIGNAL Clk_acombout : std_logic;
SIGNAL Hold_acombout : std_logic;
SIGNAL inst1_aadd_a149 : std_logic;
SIGNAL Reset_acombout : std_logic;
SIGNAL inst1_aNum_a0_a : std_logic;
SIGNAL inst1_aadd_a151 : std_logic;
SIGNAL inst1_aadd_a151COUT1_155 : std_logic;
SIGNAL inst1_aadd_a144 : std_logic;
SIGNAL inst1_aNum_a1_a : std_logic;
SIGNAL inst_aSelect_a500 : std_logic;
SIGNAL inst1_aLessThan_a56 : std_logic;
SIGNAL inst1_aadd_a146 : std_logic;
SIGNAL inst1_aadd_a146COUT1_156 : std_logic;
SIGNAL inst1_aadd_a139 : std_logic;
SIGNAL inst1_aNum_a2_a : std_logic;
SIGNAL inst1_aadd_a141 : std_logic;
SIGNAL inst1_aadd_a141COUT1 : std_logic;
SIGNAL inst1_aadd_a134 : std_logic;
SIGNAL inst1_aNum_a3_a : std_logic;
SIGNAL inst1_aadd_a136 : std_logic;
SIGNAL inst1_aadd_a131 : std_logic;
SIGNAL inst1_aadd_a131COUT1_157 : std_logic;
SIGNAL inst1_aadd_a124 : std_logic;
SIGNAL inst1_aNum_a5_a : std_logic;
SIGNAL inst1_aNum_a5_a_a718 : std_logic;
SIGNAL inst1_aNum_a5_a_a733 : std_logic;
SIGNAL inst1_aadd_a129 : std_logic;
SIGNAL inst1_aNum_a4_a : std_logic;
SIGNAL inst_areduce_nor_a59 : std_logic;
SIGNAL inst_areduce_nor_a2 : std_logic;
SIGNAL inst_areduce_nor_a60 : std_logic;
SIGNAL inst_aSelect_a503 : std_logic;
SIGNAL inst_aSelect_a505 : std_logic;
SIGNAL inst_aSelect_a506 : std_logic;
SIGNAL inst_aSelect_a509 : std_logic;
SIGNAL inst_aState_as1 : std_logic;
SIGNAL inst_aSelect_a504 : std_logic;
SIGNAL inst_aState_as2 : std_logic;
SIGNAL inst_aSelect_a502 : std_logic;
SIGNAL inst_aSelect_a507 : std_logic;
SIGNAL inst_aState_as3 : std_logic;
SIGNAL inst_aSelect_a501 : std_logic;
SIGNAL inst_aState_as0 : std_logic;
SIGNAL inst_aGA_a3 : std_logic;
SIGNAL inst_aGB_a10 : std_logic;
SIGNAL inst_aYA_a10 : std_logic;
SIGNAL inst_aYB_a10 : std_logic;
SIGNAL inst_aRA_a13 : std_logic;
SIGNAL inst_aRB_a3 : std_logic;
SIGNAL ALT_INV_Clk_acombout : std_logic;
SIGNAL ALT_INV_inst_aGA_a3 : std_logic;
COMPONENT cyclone_lcell
PORT (
	clk : IN STD_LOGIC;
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cin0 : IN STD_LOGIC;
	cin1 : IN STD_LOGIC;
	inverta : IN STD_LOGIC;
	regcascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cout0 : OUT STD_LOGIC;
	cout1 : OUT STD_LOGIC;
	MODESEL : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
	PATHSEL : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	ENABLE_ASYNCH_ARCS : IN STD_LOGIC);
END COMPONENT;

COMPONENT cyclone_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	MODESEL : IN STD_LOGIC_VECTOR(26 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_Hold <= Hold;
ww_Clk <= Clk;
ww_Reset <= Reset;
GA <= ww_GA;
GB <= ww_GB;
YA <= ww_YA;
YB <= ww_YB;
RA <= ww_RA;
RB <= ww_RB;
num <= ww_num;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

Clk_aI_modesel <= "000000000000000000000000001";
Hold_aI_modesel <= "000000000000000000000000001";
inst1_aadd_a149_I_modesel <= "1001001010110";
inst1_aadd_a149_I_pathsel <= "00100000010";
Reset_aI_modesel <= "000000000000000000000000001";
inst1_aNum_a0_a_aI_modesel <= "1100001010101";
inst1_aNum_a0_a_aI_pathsel <= "00000001111";
inst1_aadd_a144_I_modesel <= "1001010010110";
inst1_aadd_a144_I_pathsel <= "01010010001";
inst1_aNum_a1_a_aI_modesel <= "1100001010101";
inst1_aNum_a1_a_aI_pathsel <= "00000001111";
inst_aSelect_a500_I_modesel <= "1001001010101";
inst_aSelect_a500_I_pathsel <= "00000001111";
inst1_aLessThan_a56_I_modesel <= "1001001010101";
inst1_aLessThan_a56_I_pathsel <= "00000001110";
inst1_aadd_a139_I_modesel <= "1001010010110";
inst1_aadd_a139_I_pathsel <= "01100010010";
inst1_aNum_a2_a_aI_modesel <= "1100001010101";
inst1_aNum_a2_a_aI_pathsel <= "00000001111";
inst1_aadd_a134_I_modesel <= "1001010010110";
inst1_aadd_a134_I_pathsel <= "01100010010";
inst1_aNum_a3_a_aI_modesel <= "1100001010101";
inst1_aNum_a3_a_aI_pathsel <= "00000001111";
inst1_aadd_a129_I_modesel <= "1001010010110";
inst1_aadd_a129_I_pathsel <= "01010010001";
inst1_aadd_a124_I_modesel <= "1001010010101";
inst1_aadd_a124_I_pathsel <= "00000011000";
inst1_aNum_a5_a_aI_modesel <= "1100001010101";
inst1_aNum_a5_a_aI_pathsel <= "00000001111";
inst1_aNum_a5_a_a718_I_modesel <= "1001001010101";
inst1_aNum_a5_a_a718_I_pathsel <= "00000001101";
inst1_aNum_a5_a_a733_I_modesel <= "1001001010101";
inst1_aNum_a5_a_a733_I_pathsel <= "00000001111";
inst1_aNum_a4_a_aI_modesel <= "1100001010101";
inst1_aNum_a4_a_aI_pathsel <= "00000001111";
inst_areduce_nor_a59_I_modesel <= "1001001010101";
inst_areduce_nor_a59_I_pathsel <= "00000000111";
inst_areduce_nor_a2_I_modesel <= "1001001010101";
inst_areduce_nor_a2_I_pathsel <= "00000001111";
inst_areduce_nor_a60_I_modesel <= "1001001010101";
inst_areduce_nor_a60_I_pathsel <= "00000001111";
inst_aSelect_a503_I_modesel <= "1001001010101";
inst_aSelect_a503_I_pathsel <= "00000001100";
inst_aSelect_a505_I_modesel <= "1001001010101";
inst_aSelect_a505_I_pathsel <= "00000001011";
inst_aSelect_a506_I_modesel <= "1001001010101";
inst_aSelect_a506_I_pathsel <= "00000001111";
inst_aSelect_a509_I_modesel <= "1001001010101";
inst_aSelect_a509_I_pathsel <= "00000001111";
inst_aState_as1_aI_modesel <= "1100001010101";
inst_aState_as1_aI_pathsel <= "00000001111";
inst_aSelect_a504_I_modesel <= "1001001010101";
inst_aSelect_a504_I_pathsel <= "00000001111";
inst_aState_as2_aI_modesel <= "1100001010101";
inst_aState_as2_aI_pathsel <= "00000001111";
inst_aSelect_a502_I_modesel <= "1001001010101";
inst_aSelect_a502_I_pathsel <= "00000001001";
inst_aSelect_a507_I_modesel <= "1001001010101";
inst_aSelect_a507_I_pathsel <= "00000001111";
inst_aState_as3_aI_modesel <= "1100001010101";
inst_aState_as3_aI_pathsel <= "00000000100";
inst_aSelect_a501_I_modesel <= "1001001010101";
inst_aSelect_a501_I_pathsel <= "00000001111";
inst_aState_as0_aI_modesel <= "1100001010101";
inst_aState_as0_aI_pathsel <= "00000001000";
inst_aGA_a3_I_modesel <= "1001001010101";
inst_aGA_a3_I_pathsel <= "00000001100";
inst_aGB_a10_I_modesel <= "1001001010101";
inst_aGB_a10_I_pathsel <= "00000000110";
inst_aYA_a10_I_modesel <= "1001001010101";
inst_aYA_a10_I_pathsel <= "00000000101";
inst_aYB_a10_I_modesel <= "1001001010101";
inst_aYB_a10_I_pathsel <= "00000001100";
inst_aRA_a13_I_modesel <= "1001001010101";
inst_aRA_a13_I_pathsel <= "00000001101";
inst_aRB_a3_I_modesel <= "1001001010101";
inst_aRB_a3_I_pathsel <= "00000001101";
GA_aI_modesel <= "000000000000000000000000010";
GB_aI_modesel <= "000000000000000000000000010";
YA_aI_modesel <= "000000000000000000000000010";
YB_aI_modesel <= "000000000000000000000000010";
RA_aI_modesel <= "000000000000000000000000010";
RB_aI_modesel <= "000000000000000000000000010";
num_a5_a_aI_modesel <= "000000000000000000000000010";
num_a4_a_aI_modesel <= "000000000000000000000000010";
num_a3_a_aI_modesel <= "000000000000000000000000010";
num_a2_a_aI_modesel <= "000000000000000000000000010";
num_a1_a_aI_modesel <= "000000000000000000000000010";
num_a0_a_aI_modesel <= "000000000000000000000000010";

INV_INST_Clk_acombout : INV
PORT MAP (
	 IN1 => Clk_acombout,
	 Y => ALT_INV_Clk_acombout);

INV_INST_inst_aGA_a3 : INV
PORT MAP (
	 IN1 => inst_aGA_a3,
	 Y => ALT_INV_inst_aGA_a3);

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

Clk_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => Clk_aI_modesel,
	combout => Clk_acombout,
	padio => ww_Clk);

Hold_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => Hold_aI_modesel,
	combout => Hold_acombout,
	padio => ww_Hold);

inst1_aadd_a149_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a149 = !inst1_aNum_a0_a
-- inst1_aadd_a151 = CARRY(inst1_aNum_a0_a)
-- inst1_aadd_a151COUT1_155 = CARRY(inst1_aNum_a0_a)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "33CC",
--	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aadd_a149_I_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => inst1_aNum_a0_a,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => inst1_aadd_a149_I_modesel,
	combout => inst1_aadd_a149,
	cout0 => inst1_aadd_a151,
	cout1 => inst1_aadd_a151COUT1_155);

Reset_aI : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => Reset_aI_modesel,
	combout => Reset_acombout,
	padio => ww_Reset);

inst1_aNum_a0_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a0_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a0_a) # !inst1_aNum_a5_a_a733 & inst1_aadd_a149 & (inst1_aLessThan_a56), GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "CCA0",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => inst1_aNum_a0_a_aI_pathsel,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => Clk_acombout,
	dataa => inst1_aadd_a149,
	datab => inst1_aNum_a0_a,