jiaotongdeng.vho

用VHDL做的交通灯设计

inst_aState_as0_aI : cyclone_lcell
-- Equation(s):
-- inst_aState_as0 = DFFEAS(!inst_aSelect_a501, !GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , inst_aSelect_a507, , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "00FF",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => ALT_INV_Clk_acombout,
	datad => inst_aSelect_a501,
	aclr => Reset_acombout,
	ena => inst_aSelect_a507,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst_aState_as0);

inst_aGA_a3_I : cyclone_lcell
-- Equation(s):
-- inst_aGA_a3 = Hold_acombout # inst_aState_as0

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => Hold_acombout,
	datad => inst_aState_as0,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aGA_a3);

inst_aGB_a10_I : cyclone_lcell
-- Equation(s):
-- inst_aGB_a10 = inst_aState_as2 & !Hold_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0C0C",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => inst_aState_as2,
	datac => Hold_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aGB_a10);

inst_aYA_a10_I : cyclone_lcell
-- Equation(s):
-- inst_aYA_a10 = inst_aState_as1 & (!Hold_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0A0A",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst_aState_as1,
	datac => Hold_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aYA_a10);

inst_aYB_a10_I : cyclone_lcell
-- Equation(s):
-- inst_aYB_a10 = !Hold_acombout & inst_aState_as3

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => Hold_acombout,
	datad => inst_aState_as3,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aYB_a10);

inst_aRA_a13_I : cyclone_lcell
-- Equation(s):
-- inst_aRA_a13 = Hold_acombout # !inst_aState_as1 & inst_aState_as0

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F5F0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst_aState_as1,
	datac => Hold_acombout,
	datad => inst_aState_as0,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aRA_a13);

inst_aRB_a3_I : cyclone_lcell
-- Equation(s):
-- inst_aRB_a3 = inst_aState_as1 # Hold_acombout # !inst_aState_as0

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FAFF",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst_aState_as1,
	datac => Hold_acombout,
	datad => inst_aState_as0,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aRB_a3);

GA_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_inst_aGA_a3,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_GA);

GB_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst_aGB_a10,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_GB);

YA_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst_aYA_a10,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_YA);

YB_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst_aYB_a10,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_YB);

RA_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst_aRA_a13,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_RA);

RB_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst_aRB_a3,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_RB);

num_a5_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst1_aNum_a5_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_num(5));

num_a4_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst1_aNum_a4_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_num(4));

num_a3_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst1_aNum_a3_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_num(3));

num_a2_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst1_aNum_a2_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_num(2));

num_a1_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst1_aNum_a1_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_num(1));

num_a0_a_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => inst1_aNum_a0_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_num(0));
END structure;