jiaotongdeng.vho

用VHDL做的交通灯设计

	devpor => ww_devpor,
	regout => inst1_aNum_a3_a);

inst1_aadd_a129_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a129 = inst1_aNum_a4_a $ (!(!inst1_aadd_a136 & GND) # (inst1_aadd_a136 & VCC))
-- inst1_aadd_a131 = CARRY(inst1_aNum_a4_a & (!inst1_aadd_a136))
-- inst1_aadd_a131COUT1_157 = CARRY(inst1_aNum_a4_a & (!inst1_aadd_a136))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "A50A",
	cin_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a4_a,
	cin => inst1_aadd_a136,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aadd_a129,
	cout0 => inst1_aadd_a131,
	cout1 => inst1_aadd_a131COUT1_157);

inst1_aadd_a124_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a124 = (!inst1_aadd_a136 & inst1_aadd_a131) # (inst1_aadd_a136 & inst1_aadd_a131COUT1_157) $ inst1_aNum_a5_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "0FF0",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datad => inst1_aNum_a5_a,
	cin => inst1_aadd_a136,
	cin0 => inst1_aadd_a131,
	cin1 => inst1_aadd_a131COUT1_157,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aadd_a124);

inst1_aNum_a5_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a5_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a5_a) # !inst1_aNum_a5_a_a733 & inst1_aadd_a124 & inst1_aLessThan_a56, GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F088",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => Clk_acombout,
	dataa => inst1_aadd_a124,
	datab => inst1_aLessThan_a56,
	datac => inst1_aNum_a5_a,
	datad => inst1_aNum_a5_a_a733,
	aclr => Reset_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst1_aNum_a5_a);

inst1_aNum_a5_a_a718_I : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a5_a_a718 = inst1_aNum_a1_a # inst1_aNum_a2_a # inst1_aNum_a3_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFFA",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a1_a,
	datac => inst1_aNum_a2_a,
	datad => inst1_aNum_a3_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aNum_a5_a_a718);

inst1_aNum_a5_a_a733_I : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a5_a_a733 = Hold_acombout # inst1_aNum_a5_a & inst1_aNum_a5_a_a718 & inst1_aNum_a4_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "EAAA",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => Hold_acombout,
	datab => inst1_aNum_a5_a,
	datac => inst1_aNum_a5_a_a718,
	datad => inst1_aNum_a4_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aNum_a5_a_a733);

inst1_aNum_a4_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a4_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a4_a) # !inst1_aNum_a5_a_a733 & inst1_aLessThan_a56 & inst1_aadd_a129, GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "EA40",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => Clk_acombout,
	dataa => inst1_aNum_a5_a_a733,
	datab => inst1_aLessThan_a56,
	datac => inst1_aadd_a129,
	datad => inst1_aNum_a4_a,
	aclr => Reset_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst1_aNum_a4_a);

inst_areduce_nor_a59_I : cyclone_lcell
-- Equation(s):
-- inst_areduce_nor_a59 = !inst1_aNum_a1_a & inst1_aNum_a3_a & inst1_aNum_a0_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "4040",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a1_a,
	datab => inst1_aNum_a3_a,
	datac => inst1_aNum_a0_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_areduce_nor_a59);

inst_areduce_nor_a2_I : cyclone_lcell
-- Equation(s):
-- inst_areduce_nor_a2 = inst1_aNum_a4_a # !inst_areduce_nor_a59 # !inst1_aNum_a2_a # !inst1_aNum_a5_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "BFFF",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a4_a,
	datab => inst1_aNum_a5_a,
	datac => inst1_aNum_a2_a,
	datad => inst_areduce_nor_a59,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_areduce_nor_a2);

inst_areduce_nor_a60_I : cyclone_lcell
-- Equation(s):
-- inst_areduce_nor_a60 = inst1_aNum_a1_a # inst1_aNum_a2_a # !inst1_aNum_a3_a # !inst1_aNum_a0_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFBF",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a1_a,
	datab => inst1_aNum_a0_a,
	datac => inst1_aNum_a3_a,
	datad => inst1_aNum_a2_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_areduce_nor_a60);

inst_aSelect_a503_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a503 = !inst1_aNum_a5_a & inst1_aNum_a4_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => inst1_aNum_a5_a,
	datad => inst1_aNum_a4_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a503);

inst_aSelect_a505_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a505 = !inst1_aNum_a1_a & !inst1_aNum_a0_a & (!inst1_aNum_a3_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0011",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a1_a,
	datab => inst1_aNum_a0_a,
	datad => inst1_aNum_a3_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a505);

inst_aSelect_a506_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a506 = inst1_aNum_a2_a & inst_aSelect_a503 & !inst_aState_as0 & inst_aSelect_a505

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0800",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a2_a,
	datab => inst_aSelect_a503,
	datac => inst_aState_as0,
	datad => inst_aSelect_a505,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a506);

inst_aSelect_a509_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a509 = inst_aState_as1 & (inst_areduce_nor_a60 # !inst_aSelect_a503) # !inst_aState_as1 & (inst_aSelect_a506)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "ACFC",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst_areduce_nor_a60,
	datab => inst_aSelect_a506,
	datac => inst_aState_as1,
	datad => inst_aSelect_a503,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a509);

inst_aState_as1_aI : cyclone_lcell
-- Equation(s):
-- inst_aState_as1 = DFFEAS(!inst_aSelect_a501 & inst_aSelect_a509 & (inst_areduce_nor_a2 # !inst_aState_as2), !GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3100",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => ALT_INV_Clk_acombout,
	dataa => inst_aState_as2,
	datab => inst_aSelect_a501,
	datac => inst_areduce_nor_a2,
	datad => inst_aSelect_a509,
	aclr => Reset_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst_aState_as1);

inst_aSelect_a504_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a504 = inst1_aNum_a2_a # !inst_aSelect_a503 # !inst_aState_as1 # !inst_areduce_nor_a59

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "BFFF",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a2_a,
	datab => inst_areduce_nor_a59,
	datac => inst_aState_as1,
	datad => inst_aSelect_a503,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a504);

inst_aState_as2_aI : cyclone_lcell
-- Equation(s):
-- inst_aState_as2 = DFFEAS(!inst_aSelect_a501 & (inst_aState_as2 & (inst_areduce_nor_a2) # !inst_aState_as2 & !inst_aSelect_a504), !GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "3101",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => ALT_INV_Clk_acombout,
	dataa => inst_aSelect_a504,
	datab => inst_aSelect_a501,
	datac => inst_aState_as2,
	datad => inst_areduce_nor_a2,
	aclr => Reset_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst_aState_as2);

inst_aSelect_a502_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a502 = inst_areduce_nor_a2 # !inst_aState_as2

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "AAFF",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst_areduce_nor_a2,
	datad => inst_aState_as2,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a502);

inst_aSelect_a507_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a507 = inst_aSelect_a502 $ inst_aSelect_a504 $ inst_aSelect_a506 $ inst_aSelect_a501

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "6996",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst_aSelect_a502,
	datab => inst_aSelect_a504,
	datac => inst_aSelect_a506,
	datad => inst_aSelect_a501,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a507);

inst_aState_as3_aI : cyclone_lcell
-- Equation(s):
-- inst_aState_as3 = DFFEAS(!inst_aSelect_a502, !GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , inst_aSelect_a507, , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => ALT_INV_Clk_acombout,
	datac => inst_aSelect_a502,
	aclr => Reset_acombout,
	ena => inst_aSelect_a507,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst_aState_as3);

inst_aSelect_a501_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a501 = inst_aState_as3 & !inst1_aNum_a5_a & !inst1_aNum_a4_a & inst_aSelect_a500

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0200",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst_aState_as3,
	datab => inst1_aNum_a5_a,
	datac => inst1_aNum_a4_a,
	datad => inst_aSelect_a500,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a501);