jiaotongdeng.vho

用VHDL做的交通灯设计

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

-- DATE "04/08/2008 11:41:14"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	jiaotongdeng IS
    PORT (
	Hold : IN std_logic;
	Clk : IN std_logic;
	Reset : IN std_logic;
	GA : OUT std_logic;
	GB : OUT std_logic;
	YA : OUT std_logic;
	YB : OUT std_logic;
	RA : OUT std_logic;
	RB : OUT std_logic;
	num : OUT std_logic_vector(5 DOWNTO 0)
	);
END jiaotongdeng;

ARCHITECTURE structure OF jiaotongdeng IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_Hold : std_logic;
SIGNAL ww_Clk : std_logic;
SIGNAL ww_Reset : std_logic;
SIGNAL ww_GA : std_logic;
SIGNAL ww_GB : std_logic;
SIGNAL ww_YA : std_logic;
SIGNAL ww_YB : std_logic;
SIGNAL ww_RA : std_logic;
SIGNAL ww_RB : std_logic;
SIGNAL ww_num : std_logic_vector(5 DOWNTO 0);
SIGNAL Clk_acombout : std_logic;
SIGNAL Hold_acombout : std_logic;
SIGNAL inst1_aadd_a149 : std_logic;
SIGNAL Reset_acombout : std_logic;
SIGNAL inst1_aNum_a0_a : std_logic;
SIGNAL inst1_aadd_a151 : std_logic;
SIGNAL inst1_aadd_a151COUT1_155 : std_logic;
SIGNAL inst1_aadd_a144 : std_logic;
SIGNAL inst1_aNum_a1_a : std_logic;
SIGNAL inst_aSelect_a500 : std_logic;
SIGNAL inst1_aLessThan_a56 : std_logic;
SIGNAL inst1_aadd_a146 : std_logic;
SIGNAL inst1_aadd_a146COUT1_156 : std_logic;
SIGNAL inst1_aadd_a139 : std_logic;
SIGNAL inst1_aNum_a2_a : std_logic;
SIGNAL inst1_aadd_a141 : std_logic;
SIGNAL inst1_aadd_a141COUT1 : std_logic;
SIGNAL inst1_aadd_a134 : std_logic;
SIGNAL inst1_aNum_a3_a : std_logic;
SIGNAL inst1_aadd_a136 : std_logic;
SIGNAL inst1_aadd_a131 : std_logic;
SIGNAL inst1_aadd_a131COUT1_157 : std_logic;
SIGNAL inst1_aadd_a124 : std_logic;
SIGNAL inst1_aNum_a5_a : std_logic;
SIGNAL inst1_aNum_a5_a_a718 : std_logic;
SIGNAL inst1_aNum_a5_a_a733 : std_logic;
SIGNAL inst1_aadd_a129 : std_logic;
SIGNAL inst1_aNum_a4_a : std_logic;
SIGNAL inst_areduce_nor_a59 : std_logic;
SIGNAL inst_areduce_nor_a2 : std_logic;
SIGNAL inst_areduce_nor_a60 : std_logic;
SIGNAL inst_aSelect_a503 : std_logic;
SIGNAL inst_aSelect_a505 : std_logic;
SIGNAL inst_aSelect_a506 : std_logic;
SIGNAL inst_aSelect_a509 : std_logic;
SIGNAL inst_aState_as1 : std_logic;
SIGNAL inst_aSelect_a504 : std_logic;
SIGNAL inst_aState_as2 : std_logic;
SIGNAL inst_aSelect_a502 : std_logic;
SIGNAL inst_aSelect_a507 : std_logic;
SIGNAL inst_aState_as3 : std_logic;
SIGNAL inst_aSelect_a501 : std_logic;
SIGNAL inst_aState_as0 : std_logic;
SIGNAL inst_aGA_a3 : std_logic;
SIGNAL inst_aGB_a10 : std_logic;
SIGNAL inst_aYA_a10 : std_logic;
SIGNAL inst_aYB_a10 : std_logic;
SIGNAL inst_aRA_a13 : std_logic;
SIGNAL inst_aRB_a3 : std_logic;
SIGNAL ALT_INV_inst_aGA_a3 : std_logic;
SIGNAL ALT_INV_Clk_acombout : std_logic;

BEGIN

ww_Hold <= Hold;
ww_Clk <= Clk;
ww_Reset <= Reset;
GA <= ww_GA;
GB <= ww_GB;
YA <= ww_YA;
YB <= ww_YB;
RA <= ww_RA;
RB <= ww_RB;
num <= ww_num;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
ALT_INV_inst_aGA_a3 <= NOT inst_aGA_a3;
ALT_INV_Clk_acombout <= NOT Clk_acombout;

Clk_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_Clk,
	combout => Clk_acombout);

Hold_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_Hold,
	combout => Hold_acombout);

inst1_aadd_a149_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a149 = !inst1_aNum_a0_a
-- inst1_aadd_a151 = CARRY(inst1_aNum_a0_a)
-- inst1_aadd_a151COUT1_155 = CARRY(inst1_aNum_a0_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "33CC",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => inst1_aNum_a0_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aadd_a149,
	cout0 => inst1_aadd_a151,
	cout1 => inst1_aadd_a151COUT1_155);

Reset_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_Reset,
	combout => Reset_acombout);

inst1_aNum_a0_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a0_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a0_a) # !inst1_aNum_a5_a_a733 & inst1_aadd_a149 & (inst1_aLessThan_a56), GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "CCA0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => Clk_acombout,
	dataa => inst1_aadd_a149,
	datab => inst1_aNum_a0_a,
	datac => inst1_aLessThan_a56,
	datad => inst1_aNum_a5_a_a733,
	aclr => Reset_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst1_aNum_a0_a);

inst1_aadd_a144_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a144 = inst1_aNum_a1_a $ (inst1_aadd_a151)
-- inst1_aadd_a146 = CARRY(!inst1_aadd_a151 # !inst1_aNum_a1_a)
-- inst1_aadd_a146COUT1_156 = CARRY(!inst1_aadd_a151COUT1_155 # !inst1_aNum_a1_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "5A5F",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a1_a,
	cin0 => inst1_aadd_a151,
	cin1 => inst1_aadd_a151COUT1_155,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aadd_a144,
	cout0 => inst1_aadd_a146,
	cout1 => inst1_aadd_a146COUT1_156);

inst1_aNum_a1_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a1_a = DFFEAS(inst1_aNum_a5_a_a733 & inst1_aNum_a1_a # !inst1_aNum_a5_a_a733 & (inst1_aadd_a144 & inst1_aLessThan_a56), GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "AAC0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => Clk_acombout,
	dataa => inst1_aNum_a1_a,
	datab => inst1_aadd_a144,
	datac => inst1_aLessThan_a56,
	datad => inst1_aNum_a5_a_a733,
	aclr => Reset_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst1_aNum_a1_a);

inst_aSelect_a500_I : cyclone_lcell
-- Equation(s):
-- inst_aSelect_a500 = !inst1_aNum_a2_a & !inst1_aNum_a0_a & !inst1_aNum_a3_a & !inst1_aNum_a1_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0001",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => inst1_aNum_a2_a,
	datab => inst1_aNum_a0_a,
	datac => inst1_aNum_a3_a,
	datad => inst1_aNum_a1_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst_aSelect_a500);

inst1_aLessThan_a56_I : cyclone_lcell
-- Equation(s):
-- inst1_aLessThan_a56 = inst_aSelect_a500 # !inst1_aNum_a4_a # !inst1_aNum_a5_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "CFFF",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => inst_aSelect_a500,
	datac => inst1_aNum_a5_a,
	datad => inst1_aNum_a4_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aLessThan_a56);

inst1_aadd_a139_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a139 = inst1_aNum_a2_a $ !inst1_aadd_a146
-- inst1_aadd_a141 = CARRY(inst1_aNum_a2_a & !inst1_aadd_a146)
-- inst1_aadd_a141COUT1 = CARRY(inst1_aNum_a2_a & !inst1_aadd_a146COUT1_156)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "C30C",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => inst1_aNum_a2_a,
	cin0 => inst1_aadd_a146,
	cin1 => inst1_aadd_a146COUT1_156,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aadd_a139,
	cout0 => inst1_aadd_a141,
	cout1 => inst1_aadd_a141COUT1);

inst1_aNum_a2_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a2_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a2_a) # !inst1_aNum_a5_a_a733 & inst1_aLessThan_a56 & inst1_aadd_a139, GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F088",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => Clk_acombout,
	dataa => inst1_aLessThan_a56,
	datab => inst1_aadd_a139,
	datac => inst1_aNum_a2_a,
	datad => inst1_aNum_a5_a_a733,
	aclr => Reset_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => inst1_aNum_a2_a);

inst1_aadd_a134_I : cyclone_lcell
-- Equation(s):
-- inst1_aadd_a134 = inst1_aNum_a3_a $ inst1_aadd_a141
-- inst1_aadd_a136 = 

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "3C3F",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => inst1_aNum_a3_a,
	cin0 => inst1_aadd_a141,
	cin1 => inst1_aadd_a141COUT1,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => inst1_aadd_a134,
	cout => inst1_aadd_a136);

inst1_aNum_a3_a_aI : cyclone_lcell
-- Equation(s):
-- inst1_aNum_a3_a = DFFEAS(inst1_aNum_a5_a_a733 & (inst1_aNum_a3_a) # !inst1_aNum_a5_a_a733 & inst1_aadd_a134 & inst1_aLessThan_a56, GLOBAL(Clk_acombout), !GLOBAL(Reset_acombout), , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "EA40",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => Clk_acombout,
	dataa => inst1_aNum_a5_a_a733,
	datab => inst1_aadd_a134,
	datac => inst1_aLessThan_a56,
	datad => inst1_aNum_a3_a,
	aclr => Reset_acombout,
	devclrn => ww_devclrn,