ppm_tf.vhd

ppm编码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity test is
end ;

architecture behav of test is
 component ppm  
  port(  clk  :in std_logic;
         RST  :in std_logic;
         din  : in std_logic;
         d_en  :out std_logic;
         f_en  :out std_logic;
         dout: out std_logic);
 end component;

 signal clk,rst,din: std_logic;
 signal dout:  std_logic;
 signal d_en, f_en: std_logic;

begin
  uut_a: ppm port map (clk,rst,din,d_en,f_en,dout);
  
clk1:  process
  begin
    clk <='0';
    wait for 0.295 us;
    clk <='1';
    wait for 0.295 us;
  end process ;

rst<='0', '1' after 5.20 ns;
process
 begin
    din<='1';wait for 6.195 us;
    din<='0';wait for 9.44 us;din<='1';wait for 37.76 us;din<='0';wait for 9.44 us;
    din<='1';wait for 18.88 us;

    din<='1';wait for 28.32 us;din<='0';wait for 9.44 us;din<='1';wait for 37.76 us;
    din<='1';wait for 47.20 us;din<='0';wait for 9.44 us;din<='1';wait for 18.88 us;
    din<='1';wait for 9.44 us;din<='0';wait for 9.44 us;din<='1';wait for 56.64 us;
    din<='1';wait for 66.08 us;din<='0';wait for 9.44 us;
    din<='1';wait for 18.88 us;din<='0';wait for 9.44 us;din<='1';wait for 9.44 us; 
    din<='1'; wait for 1000 us;
end process;
end behav;

configuration cfg_tb_ppm of test is
for behav
end for;
end;