prev_cmp_crc2.fit.qmsg

基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验

{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "73 73 " "Warning: No exact pin location assignment(s) for 73 pins of 73 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "co " "Info: Pin co not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { co } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 224 1576 1752 240 "co" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { co } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { co } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[23\] " "Info: Pin m1_out\[23\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[23] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[23] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[22\] " "Info: Pin m1_out\[22\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[22] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[22] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[21\] " "Info: Pin m1_out\[21\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[21] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[21] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[20\] " "Info: Pin m1_out\[20\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[20] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[20] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[19\] " "Info: Pin m1_out\[19\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[19] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[19] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[18\] " "Info: Pin m1_out\[18\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[18] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[18] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[17\] " "Info: Pin m1_out\[17\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[17] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[17] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[16\] " "Info: Pin m1_out\[16\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[16] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[16] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[15\] " "Info: Pin m1_out\[15\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[15] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[15] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[14\] " "Info: Pin m1_out\[14\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[14] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[14] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[13\] " "Info: Pin m1_out\[13\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[13] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[13] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[12\] " "Info: Pin m1_out\[12\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[12] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[12] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[11\] " "Info: Pin m1_out\[11\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[11] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[11] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[10\] " "Info: Pin m1_out\[10\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[10] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[10] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[9\] " "Info: Pin m1_out\[9\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[9] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[9] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[8\] " "Info: Pin m1_out\[8\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[8] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[8] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[7\] " "Info: Pin m1_out\[7\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[7] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[7] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[6\] " "Info: Pin m1_out\[6\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[6] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[6] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[5\] " "Info: Pin m1_out\[5\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[5] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[5] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[4\] " "Info: Pin m1_out\[4\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[4] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[4] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[3\] " "Info: Pin m1_out\[3\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[3] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[2\] " "Info: Pin m1_out\[2\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[2] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[1\] " "Info: Pin m1_out\[1\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[1] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m1_out\[0\] " "Info: Pin m1_out\[0\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m1_out[0] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m1_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m4_out\[7\] " "Info: Pin m4_out\[7\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m4_out[7] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 184 1576 1752 200 "m4_out\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[7] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m4_out\[6\] " "Info: Pin m4_out\[6\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m4_out[6] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 184 1576 1752 200 "m4_out\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[6] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m4_out\[5\] " "Info: Pin m4_out\[5\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m4_out[5] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 184 1576 1752 200 "m4_out\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[5] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m4_out\[4\] " "Info: Pin m4_out\[4\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m4_out[4] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 184 1576 1752 200 "m4_out\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[4] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m4_out\[3\] " "Info: Pin m4_out\[3\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m4_out[3] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 184 1576 1752 200 "m4_out\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m4_out\[2\] " "Info: Pin m4_out\[2\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m4_out[2] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 184 1576 1752 200 "m4_out\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m4_out\[1\] " "Info: Pin m4_out\[1\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m4_out[1] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 184 1576 1752 200 "m4_out\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m4_out\[0\] " "Info: Pin m4_out\[0\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m4_out[0] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 184 1576 1752 200 "m4_out\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m4_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[15\] " "Info: Pin r2_out\[15\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[15] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[15] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[14\] " "Info: Pin r2_out\[14\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[14] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[14] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[13\] " "Info: Pin r2_out\[13\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[13] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[13] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[12\] " "Info: Pin r2_out\[12\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[12] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[12] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[11\] " "Info: Pin r2_out\[11\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[11] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[11] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[10\] " "Info: Pin r2_out\[10\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[10] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[10] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[9\] " "Info: Pin r2_out\[9\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[9] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[9] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[8\] " "Info: Pin r2_out\[8\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[8] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[8] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[7\] " "Info: Pin r2_out\[7\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[7] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[7] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[6\] " "Info: Pin r2_out\[6\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[6] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[6] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[5\] " "Info: Pin r2_out\[5\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[5] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[5] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[4\] " "Info: Pin r2_out\[4\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[4] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[4] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[3\] " "Info: Pin r2_out\[3\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[3] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[2\] " "Info: Pin r2_out\[2\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[2] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[1\] " "Info: Pin r2_out\[1\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[1] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r2_out\[0\] " "Info: Pin r2_out\[0\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r2_out[0] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r2_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[15\] " "Info: Pin r_out\[15\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[15] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[15] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[14\] " "Info: Pin r_out\[14\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[14] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[14] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[13\] " "Info: Pin r_out\[13\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[13] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[13] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[12\] " "Info: Pin r_out\[12\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[12] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[12] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[11\] " "Info: Pin r_out\[11\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[11] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[11] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[10\] " "Info: Pin r_out\[10\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[10] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[10] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[9\] " "Info: Pin r_out\[9\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[9] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[9] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[8\] " "Info: Pin r_out\[8\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[8] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[8] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[7\] " "Info: Pin r_out\[7\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[7] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[7] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[6\] " "Info: Pin r_out\[6\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[6] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[6] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[5\] " "Info: Pin r_out\[5\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[5] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[5] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[4\] " "Info: Pin r_out\[4\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[4] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[4] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[3\] " "Info: Pin r_out\[3\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[3] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[2\] " "Info: Pin r_out\[2\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[2] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[1\] " "Info: Pin r_out\[1\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[1] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r_out\[0\] " "Info: Pin r_out\[0\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { r_out[0] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { r_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m_in\[7\] " "Info: Pin m_in\[7\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m_in[7] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[7] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m_in\[6\] " "Info: Pin m_in\[6\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m_in[6] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[6] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m_in\[5\] " "Info: Pin m_in\[5\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m_in[5] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[5] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m_in\[4\] " "Info: Pin m_in\[4\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m_in[4] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[4] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m_in\[3\] " "Info: Pin m_in\[3\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m_in[3] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m_in\[2\] " "Info: Pin m_in\[2\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m_in[2] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m_in\[1\] " "Info: Pin m_in\[1\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m_in[1] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "m_in\[0\] " "Info: Pin m_in\[0\] not assigned to an exact location on the device" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { m_in[0] } } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}