prev_cmp_crc2.map.qmsg

基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "r4_out crc_p.vhd(23) " "Warning (10492): VHDL Process Statement warning at crc_p.vhd(23): signal \"r4_out\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "crc_p.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_p.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "crc_and2 crc_and2:inst10 " "Info: Elaborating entity \"crc_and2\" for hierarchy \"crc_and2:inst10\"" {  } { { "crc2.bdf" "inst10" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 160 1064 1248 256 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "crc_and crc_and:inst4 " "Info: Elaborating entity \"crc_and\" for hierarchy \"crc_and:inst4\"" {  } { { "crc2.bdf" "inst4" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 176 504 688 272 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "crc crc:inst " "Info: Elaborating entity \"crc\" for hierarchy \"crc:inst\"" {  } { { "crc2.bdf" "inst" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 192 224 384 288 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mm crc.vhd(20) " "Warning (10492): VHDL Process Statement warning at crc.vhd(20): signal \"mm\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../crc/crc.vhd" "" { Text "F:/FPGA_CHENGXU/crc/crc.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mm crc.vhd(29) " "Warning (10492): VHDL Process Statement warning at crc.vhd(29): signal \"mm\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../crc/crc.vhd" "" { Text "F:/FPGA_CHENGXU/crc/crc.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "crc_j crc_j:inst9 " "Info: Elaborating entity \"crc_j\" for hierarchy \"crc_j:inst9\"" {  } { { "crc2.bdf" "inst9" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 176 768 944 272 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mm crc_j.vhd(20) " "Warning (10492): VHDL Process Statement warning at crc_j.vhd(20): signal \"mm\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "crc_j.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_j.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "mm crc_j.vhd(29) " "Warning (10492): VHDL Process Statement warning at crc_j.vhd(29): signal \"mm\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "crc_j.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_j.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "co VCC " "Warning (13410): Pin \"co\" stuck at VCC" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 224 1576 1752 240 "co" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[23\] GND " "Warning (13410): Pin \"m1_out\[23\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[22\] GND " "Warning (13410): Pin \"m1_out\[22\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[21\] GND " "Warning (13410): Pin \"m1_out\[21\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[20\] GND " "Warning (13410): Pin \"m1_out\[20\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[19\] GND " "Warning (13410): Pin \"m1_out\[19\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[18\] GND " "Warning (13410): Pin \"m1_out\[18\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[17\] GND " "Warning (13410): Pin \"m1_out\[17\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[16\] GND " "Warning (13410): Pin \"m1_out\[16\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[15\] GND " "Warning (13410): Pin \"m1_out\[15\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[14\] GND " "Warning (13410): Pin \"m1_out\[14\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[13\] GND " "Warning (13410): Pin \"m1_out\[13\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[12\] GND " "Warning (13410): Pin \"m1_out\[12\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[11\] GND " "Warning (13410): Pin \"m1_out\[11\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[10\] GND " "Warning (13410): Pin \"m1_out\[10\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[9\] GND " "Warning (13410): Pin \"m1_out\[9\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[8\] GND " "Warning (13410): Pin \"m1_out\[8\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[7\] GND " "Warning (13410): Pin \"m1_out\[7\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[6\] GND " "Warning (13410): Pin \"m1_out\[6\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[5\] GND " "Warning (13410): Pin \"m1_out\[5\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[4\] GND " "Warning (13410): Pin \"m1_out\[4\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[3\] GND " "Warning (13410): Pin \"m1_out\[3\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[2\] GND " "Warning (13410): Pin \"m1_out\[2\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[1\] GND " "Warning (13410): Pin \"m1_out\[1\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m1_out\[0\] GND " "Warning (13410): Pin \"m1_out\[0\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 48 912 1088 64 "m1_out\[23..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[15\] GND " "Warning (13410): Pin \"r2_out\[15\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[14\] GND " "Warning (13410): Pin \"r2_out\[14\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[13\] GND " "Warning (13410): Pin \"r2_out\[13\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[12\] GND " "Warning (13410): Pin \"r2_out\[12\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[11\] GND " "Warning (13410): Pin \"r2_out\[11\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[10\] GND " "Warning (13410): Pin \"r2_out\[10\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[9\] GND " "Warning (13410): Pin \"r2_out\[9\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[8\] GND " "Warning (13410): Pin \"r2_out\[8\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[7\] GND " "Warning (13410): Pin \"r2_out\[7\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[6\] GND " "Warning (13410): Pin \"r2_out\[6\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[5\] GND " "Warning (13410): Pin \"r2_out\[5\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[4\] GND " "Warning (13410): Pin \"r2_out\[4\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[3\] GND " "Warning (13410): Pin \"r2_out\[3\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[2\] GND " "Warning (13410): Pin \"r2_out\[2\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[1\] GND " "Warning (13410): Pin \"r2_out\[1\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r2_out\[0\] GND " "Warning (13410): Pin \"r2_out\[0\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 112 880 1056 128 "r2_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r_out\[14\] GND " "Warning (13410): Pin \"r_out\[14\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r_out\[13\] GND " "Warning (13410): Pin \"r_out\[13\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r_out\[12\] GND " "Warning (13410): Pin \"r_out\[12\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r_out\[11\] GND " "Warning (13410): Pin \"r_out\[11\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "r_out\[10\] GND " "Warning (13410): Pin \"r_out\[10\]\" stuck at GND" {  } { { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "82 " "Info: Implemented 82 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "65 " "Info: Implemented 65 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "9 " "Info: Implemented 9 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 55 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 55 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Allocated 155 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 15 01:38:38 2008 " "Info: Processing ended: Wed Oct 15 01:38:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}