prev_cmp_crc2.tan.qmsg

基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 15 01:38:44 2008 " "Info: Processing started: Wed Oct 15 01:38:44 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off crc2 -c crc2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off crc2 -c crc2 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "m_in\[4\] r_out\[0\] 15.174 ns Longest " "Info: Longest tpd from source pin \"m_in\[4\]\" to destination pin \"r_out\[0\]\" is 15.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns m_in\[4\] 1 PIN PIN_47 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 3; PIN Node = 'm_in\[4\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_in[4] } "NODE_NAME" } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 216 -56 112 232 "m_in\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.693 ns) + CELL(0.292 ns) 8.460 ns crc:inst\|r_out\[6\]~37 2 COMB LC_X12_Y13_N5 2 " "Info: 2: + IC(6.693 ns) + CELL(0.292 ns) = 8.460 ns; Loc. = LC_X12_Y13_N5; Fanout = 2; COMB Node = 'crc:inst\|r_out\[6\]~37'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.985 ns" { m_in[4] crc:inst|r_out[6]~37 } "NODE_NAME" } } { "../crc/crc.vhd" "" { Text "F:/FPGA_CHENGXU/crc/crc.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.442 ns) 9.303 ns crc_j:inst9\|r~107 3 COMB LC_X12_Y13_N2 2 " "Info: 3: + IC(0.401 ns) + CELL(0.442 ns) = 9.303 ns; Loc. = LC_X12_Y13_N2; Fanout = 2; COMB Node = 'crc_j:inst9\|r~107'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.843 ns" { crc:inst|r_out[6]~37 crc_j:inst9|r~107 } "NODE_NAME" } } { "crc_j.vhd" "" { Text "F:/FPGA_CHENGXU/crc2/crc_j.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.292 ns) 10.037 ns crc:inst\|d\[16\]~7 4 COMB LC_X12_Y13_N3 2 " "Info: 4: + IC(0.442 ns) + CELL(0.292 ns) = 10.037 ns; Loc. = LC_X12_Y13_N3; Fanout = 2; COMB Node = 'crc:inst\|d\[16\]~7'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { crc_j:inst9|r~107 crc:inst|d[16]~7 } "NODE_NAME" } } { "../crc/crc.vhd" "" { Text "F:/FPGA_CHENGXU/crc/crc.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.029 ns) + CELL(2.108 ns) 15.174 ns r_out\[0\] 5 PIN PIN_51 0 " "Info: 5: + IC(3.029 ns) + CELL(2.108 ns) = 15.174 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'r_out\[0\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.137 ns" { crc:inst|d[16]~7 r_out[0] } "NODE_NAME" } } { "crc2.bdf" "" { Schematic "F:/FPGA_CHENGXU/crc2/crc2.bdf" { { 376 488 664 392 "r_out\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.609 ns ( 30.37 % ) " "Info: Total cell delay = 4.609 ns ( 30.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.565 ns ( 69.63 % ) " "Info: Total interconnect delay = 10.565 ns ( 69.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "15.174 ns" { m_in[4] crc:inst|r_out[6]~37 crc_j:inst9|r~107 crc:inst|d[16]~7 r_out[0] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "15.174 ns" { m_in[4] {} m_in[4]~out0 {} crc:inst|r_out[6]~37 {} crc_j:inst9|r~107 {} crc:inst|d[16]~7 {} r_out[0] {} } { 0.000ns 0.000ns 6.693ns 0.401ns 0.442ns 3.029ns } { 0.000ns 1.475ns 0.292ns 0.442ns 0.292ns 2.108ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 15 01:38:45 2008 " "Info: Processing ended: Wed Oct 15 01:38:45 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}