crc2.map.rpt

基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验

+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total logic elements                        ; 9       ;
;     -- Combinational with no register       ; 9       ;
;     -- Register only                        ; 0       ;
;     -- Combinational with a register        ; 0       ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 1       ;
;     -- 3 input functions                    ; 0       ;
;     -- 2 input functions                    ; 8       ;
;     -- 1 input functions                    ; 0       ;
;     -- 0 input functions                    ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 9       ;
;     -- arithmetic mode                      ; 0       ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 0       ;
;     -- asynchronous clear/load mode         ; 0       ;
;                                             ;         ;
; Total registers                             ; 0       ;
; I/O pins                                    ; 73      ;
; Maximum fan-out node                        ; m_in[7] ;
; Maximum fan-out                             ; 5       ;
; Total fan-out                               ; 58      ;
; Average fan-out                             ; 0.71    ;
+---------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |crc2                      ; 9 (0)       ; 0            ; 0           ; 73   ; 0            ; 9 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |crc2               ; work         ;
;    |crc:inst|              ; 6 (6)       ; 0            ; 0           ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |crc2|crc:inst      ; work         ;
;    |crc_j:inst9|           ; 3 (3)       ; 0            ; 0           ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |crc2|crc_j:inst9   ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Oct 15 01:40:09 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off crc2 -c crc2
Info: Found 2 design units, including 1 entities, in source file ../crc/crc.vhd
    Info: Found design unit 1: crc-a
    Info: Found entity 1: crc
Info: Found 1 design units, including 1 entities, in source file crc2.bdf
    Info: Found entity 1: crc2
Info: Found 2 design units, including 1 entities, in source file ../second/crc_and.vhd
    Info: Found design unit 1: crc_and-a
    Info: Found entity 1: crc_and
Info: Found 2 design units, including 1 entities, in source file crc_j.vhd
    Info: Found design unit 1: crc_j-a
    Info: Found entity 1: crc_j
Info: Found 2 design units, including 1 entities, in source file crc_p.vhd
    Info: Found design unit 1: crc_p-a
    Info: Found entity 1: crc_p
Info: Found 2 design units, including 1 entities, in source file crc_and2.vhd
    Info: Found design unit 1: crc_and2-a
    Info: Found entity 1: crc_and2
Info: Elaborating entity "crc2" for the top level hierarchy
Info: Elaborating entity "crc_p" for hierarchy "crc_p:inst6"
Warning (10492): VHDL Process Statement warning at crc_p.vhd(19): signal "r4_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at crc_p.vhd(23): signal "r4_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "crc_and2" for hierarchy "crc_and2:inst10"
Info: Elaborating entity "crc_and" for hierarchy "crc_and:inst4"
Info: Elaborating entity "crc" for hierarchy "crc:inst"
Warning (10492): VHDL Process Statement warning at crc.vhd(20): signal "mm" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at crc.vhd(29): signal "mm" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "crc_j" for hierarchy "crc_j:inst9"
Warning (10492): VHDL Process Statement warning at crc_j.vhd(20): signal "mm" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at crc_j.vhd(29): signal "mm" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "co" stuck at VCC
    Warning (13410): Pin "m1_out[14]" stuck at GND
    Warning (13410): Pin "m1_out[13]" stuck at GND
    Warning (13410): Pin "m1_out[12]" stuck at GND
    Warning (13410): Pin "m1_out[11]" stuck at GND
    Warning (13410): Pin "m1_out[10]" stuck at GND
    Warning (13410): Pin "r2_out[15]" stuck at GND
    Warning (13410): Pin "r2_out[14]" stuck at GND
    Warning (13410): Pin "r2_out[13]" stuck at GND
    Warning (13410): Pin "r2_out[12]" stuck at GND
    Warning (13410): Pin "r2_out[11]" stuck at GND
    Warning (13410): Pin "r2_out[10]" stuck at GND
    Warning (13410): Pin "r2_out[9]" stuck at GND
    Warning (13410): Pin "r2_out[8]" stuck at GND
    Warning (13410): Pin "r2_out[7]" stuck at GND
    Warning (13410): Pin "r2_out[6]" stuck at GND
    Warning (13410): Pin "r2_out[5]" stuck at GND
    Warning (13410): Pin "r2_out[4]" stuck at GND
    Warning (13410): Pin "r2_out[3]" stuck at GND
    Warning (13410): Pin "r2_out[2]" stuck at GND
    Warning (13410): Pin "r2_out[1]" stuck at GND
    Warning (13410): Pin "r2_out[0]" stuck at GND
    Warning (13410): Pin "r_out[14]" stuck at GND
    Warning (13410): Pin "r_out[13]" stuck at GND
    Warning (13410): Pin "r_out[12]" stuck at GND
    Warning (13410): Pin "r_out[11]" stuck at GND
    Warning (13410): Pin "r_out[10]" stuck at GND
Info: Implemented 82 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 65 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings
    Info: Allocated 155 megabytes of memory during processing
    Info: Processing ended: Wed Oct 15 01:40:11 2008
    Info: Elapsed time: 00:00:02