crc_and2.vhd.bak

基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验

library ieee;
use ieee.std_logic_1164.all;
entity crc_and is

port (m3_in : in std_logic_vector(7 downto 0);
      r3_out: in std_logic_vector(15 downto 0);
      m3_out: out std_logic_vector(23 downto 0)
     );
end crc_and;
architecture a of crc_and is
--signal m2_in :  std_logic_vector(m_wide downto 0);
--signal r2_out:  std_logic_vector(r_wide downto 0);
--signal m2_out:  std_logic_vector(r1_wide+m1_wide downto 0);
begin 
process(m3_in,r3_out)
begin 
m3_out<=m3_in&r3_out;
end process;
end a;