crc_j.vhd.bak

基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验

library ieee;
use ieee.std_logic_1164.all;
entity crc_j is
port (m2_in : in std_logic_vector(23 downto 0);
      r2_out: out std_logic_vector(15 downto 0)
     );
end crc_j;
architecture a of crc_j is
constant crc_wide : integer:= 23+15+1;
constant g_wide : integer:= 15+1;
signal mm : std_logic_vector(crc_wide downto 0);
constant g : std_logic_vector(g_wide downto 0):="11000000000000101";
begin
 process(m2_in)
  variable d: std_logic_vector(g_wide downto 0);
  variable r: std_logic_vector(15 downto 0);
begin
  r :=(others =>'0');
  mm<=m2_in&r;
  d :=mm(crc_wide downto (crc_wide-g_wide));
for i in (crc_wide-g_wide-1) downto 0 loop
  if d(g_wide)='0' then
     r:=d(15 downto 0);
  else
   for j in 15 downto 0 loop
    r(j):=d(j) xor g(j);
   end loop;
  end if;
  d:=r&mm(i);
end loop;
if d(g_wide)='0' then
   r:=d(15 downto 0);
else
   for j in 15 downto 0 loop
    r(j):=d(j) xor g(j);
   end loop;
end if;
r_out<=r;
end process;
end a;