crc_p.vhd

来自「基于FPGA的1CRC_16校验基于FPGA的1CRC_16校验基于FPGA的1」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
entity crc_p is

port (m4_in : in std_logic_vector(39 downto 0);
      --r4_out: in std_logic_vector(15 downto 0);
      m4_out: out std_logic_vector(7 downto 0);
      co: out std_logic
     );
end crc_p;
architecture a of crc_p is
--signal m4_in :  std_logic_vector(m_wide downto 0);
 signal r4_out:  std_logic_vector(15 downto 0);
--signal m4_out:  std_logic_vector(r1_wide+m1_wide downto 0);
begin 
process(m4_in)
begin 
r4_out<=m4_in(15 downto 0);
case r4_out is
when "0000000000000000"=>m4_out<=m4_in(39 downto 32);
when others =>m4_out<="00000000";
end case;
case r4_out is
when "0000000000000000"=>co<='1';
when others =>co<='0';
end case;
end process;
end a;