second.tan.qmsg

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "xian:inst6\|d1\[1\] xian:inst6\|data1\[4\] clk 30.77 ns " "Info: Found hold time violation between source  pin or register \"xian:inst6\|d1\[1\]\" and destination pin or register \"xian:inst6\|data1\[4\]\" for clock \"clk\" (Hold time is 30.77 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "34.404 ns + Largest " "Info: + Largest clock skew is 34.404 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 41.579 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 41.579 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 37 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 37; CLK Node = 'clk'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -64 -136 32 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns fenpin:inst\|clk1 2 REG LC_X23_Y8_N6 5 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X23_Y8_N6; Fanout = 5; REG Node = 'fenpin:inst\|clk1'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { clk fenpin:inst|clk1 } "NODE_NAME" } } { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.478 ns) + CELL(0.935 ns) 8.419 ns cnt_10:inst1\|co 3 REG LC_X19_Y10_N0 6 " "Info: 3: + IC(4.478 ns) + CELL(0.935 ns) = 8.419 ns; Loc. = LC_X19_Y10_N0; Fanout = 6; REG Node = 'cnt_10:inst1\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.413 ns" { fenpin:inst|clk1 cnt_10:inst1|co } "NODE_NAME" } } { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.768 ns) + CELL(0.935 ns) 14.122 ns cnt_10:inst2\|co 4 REG LC_X15_Y6_N9 10 " "Info: 4: + IC(4.768 ns) + CELL(0.935 ns) = 14.122 ns; Loc. = LC_X15_Y6_N9; Fanout = 10; REG Node = 'cnt_10:inst2\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.703 ns" { cnt_10:inst1|co cnt_10:inst2|co } "NODE_NAME" } } { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.348 ns) + CELL(0.935 ns) 19.405 ns cnt_60:inst3\|co 5 REG LC_X15_Y6_N2 10 " "Info: 5: + IC(4.348 ns) + CELL(0.935 ns) = 19.405 ns; Loc. = LC_X15_Y6_N2; Fanout = 10; REG Node = 'cnt_60:inst3\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { cnt_10:inst2|co cnt_60:inst3|co } "NODE_NAME" } } { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.338 ns) + CELL(0.935 ns) 24.678 ns cnt_60:inst4\|co 6 REG LC_X18_Y11_N9 9 " "Info: 6: + IC(4.338 ns) + CELL(0.935 ns) = 24.678 ns; Loc. = LC_X18_Y11_N9; Fanout = 9; REG Node = 'cnt_60:inst4\|co'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.273 ns" { cnt_60:inst3|co cnt_60:inst4|co } "NODE_NAME" } } { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.243 ns) + CELL(0.935 ns) 30.856 ns cnt_12:inst5\|QL\[2\] 7 REG LC_X19_Y11_N2 6 " "Info: 7: + IC(5.243 ns) + CELL(0.935 ns) = 30.856 ns; Loc. = LC_X19_Y11_N2; Fanout = 6; REG Node = 'cnt_12:inst5\|QL\[2\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.178 ns" { cnt_60:inst4|co cnt_12:inst5|QL[2] } "NODE_NAME" } } { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.292 ns) 31.698 ns xian:inst6\|Mux1~55 8 COMB LC_X19_Y11_N9 1 " "Info: 8: + IC(0.550 ns) + CELL(0.292 ns) = 31.698 ns; Loc. = LC_X19_Y11_N9; Fanout = 1; COMB Node = 'xian:inst6\|Mux1~55'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.842 ns" { cnt_12:inst5|QL[2] xian:inst6|Mux1~55 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.292 ns) 33.190 ns xian:inst6\|Mux1~56 9 COMB LC_X18_Y12_N5 1 " "Info: 9: + IC(1.200 ns) + CELL(0.292 ns) = 33.190 ns; Loc. = LC_X18_Y12_N5; Fanout = 1; COMB Node = 'xian:inst6\|Mux1~56'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { xian:inst6|Mux1~55 xian:inst6|Mux1~56 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.424 ns) + CELL(0.114 ns) 33.728 ns xian:inst6\|Mux1~59 10 COMB LC_X18_Y12_N1 8 " "Info: 10: + IC(0.424 ns) + CELL(0.114 ns) = 33.728 ns; Loc. = LC_X18_Y12_N1; Fanout = 8; COMB Node = 'xian:inst6\|Mux1~59'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.538 ns" { xian:inst6|Mux1~56 xian:inst6|Mux1~59 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.154 ns) + CELL(0.292 ns) 35.174 ns xian:inst6\|Mux22~55 11 COMB LC_X20_Y12_N2 7 " "Info: 11: + IC(1.154 ns) + CELL(0.292 ns) = 35.174 ns; Loc. = LC_X20_Y12_N2; Fanout = 7; COMB Node = 'xian:inst6\|Mux22~55'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.446 ns" { xian:inst6|Mux1~59 xian:inst6|Mux22~55 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.113 ns) + CELL(0.292 ns) 41.579 ns xian:inst6\|data1\[4\] 12 REG LC_X19_Y12_N8 1 " "Info: 12: + IC(6.113 ns) + CELL(0.292 ns) = 41.579 ns; Loc. = LC_X19_Y12_N8; Fanout = 1; REG Node = 'xian:inst6\|data1\[4\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.405 ns" { xian:inst6|Mux22~55 xian:inst6|data1[4] } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.361 ns ( 20.11 % ) " "Info: Total cell delay = 8.361 ns ( 20.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "33.218 ns ( 79.89 % ) " "Info: Total interconnect delay = 33.218 ns ( 79.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "41.579 ns" { clk fenpin:inst|clk1 cnt_10:inst1|co cnt_10:inst2|co cnt_60:inst3|co cnt_60:inst4|co cnt_12:inst5|QL[2] xian:inst6|Mux1~55 xian:inst6|Mux1~56 xian:inst6|Mux1~59 xian:inst6|Mux22~55 xian:inst6|data1[4] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "41.579 ns" { clk {} clk~out0 {} fenpin:inst|clk1 {} cnt_10:inst1|co {} cnt_10:inst2|co {} cnt_60:inst3|co {} cnt_60:inst4|co {} cnt_12:inst5|QL[2] {} xian:inst6|Mux1~55 {} xian:inst6|Mux1~56 {} xian:inst6|Mux1~59 {} xian:inst6|Mux22~55 {} xian:inst6|data1[4] {} } { 0.000ns 0.000ns 0.602ns 4.478ns 4.768ns 4.348ns 4.338ns 5.243ns 0.550ns 1.200ns 0.424ns 1.154ns 6.113ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.292ns 0.292ns 0.114ns 0.292ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.175 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 37 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 37; CLK Node = 'clk'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -64 -136 32 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns fp2:inst12\|clk1 2 REG LC_X8_Y6_N4 3 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N4; Fanout = 3; REG Node = 'fp2:inst12\|clk1'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk fp2:inst12|clk1 } "NODE_NAME" } } { "fp2.vhd" "" { Text "F:/FPGA_CHENGXU/second/fp2.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.711 ns) 7.175 ns xian:inst6\|d1\[1\] 3 REG LC_X18_Y11_N5 23 " "Info: 3: + IC(3.500 ns) + CELL(0.711 ns) = 7.175 ns; Loc. = LC_X18_Y11_N5; Fanout = 23; REG Node = 'xian:inst6\|d1\[1\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.211 ns" { fp2:inst12|clk1 xian:inst6|d1[1] } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.41 % ) " "Info: Total cell delay = 3.115 ns ( 43.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.060 ns ( 56.59 % ) " "Info: Total interconnect delay = 4.060 ns ( 56.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.175 ns" { clk fp2:inst12|clk1 xian:inst6|d1[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.175 ns" { clk {} clk~out0 {} fp2:inst12|clk1 {} xian:inst6|d1[1] {} } { 0.000ns 0.000ns 0.560ns 3.500ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "41.579 ns" { clk fenpin:inst|clk1 cnt_10:inst1|co cnt_10:inst2|co cnt_60:inst3|co cnt_60:inst4|co cnt_12:inst5|QL[2] xian:inst6|Mux1~55 xian:inst6|Mux1~56 xian:inst6|Mux1~59 xian:inst6|Mux22~55 xian:inst6|data1[4] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "41.579 ns" { clk {} clk~out0 {} fenpin:inst|clk1 {} cnt_10:inst1|co {} cnt_10:inst2|co {} cnt_60:inst3|co {} cnt_60:inst4|co {} cnt_12:inst5|QL[2] {} xian:inst6|Mux1~55 {} xian:inst6|Mux1~56 {} xian:inst6|Mux1~59 {} xian:inst6|Mux22~55 {} xian:inst6|data1[4] {} } { 0.000ns 0.000ns 0.602ns 4.478ns 4.768ns 4.348ns 4.338ns 5.243ns 0.550ns 1.200ns 0.424ns 1.154ns 6.113ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.292ns 0.292ns 0.114ns 0.292ns 0.292ns } "" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.175 ns" { clk fp2:inst12|clk1 xian:inst6|d1[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.175 ns" { clk {} clk~out0 {} fp2:inst12|clk1 {} xian:inst6|d1[1] {} } { 0.000ns 0.000ns 0.560ns 3.500ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.410 ns - Shortest register register " "Info: - Shortest register to register delay is 3.410 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xian:inst6\|d1\[1\] 1 REG LC_X18_Y11_N5 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y11_N5; Fanout = 23; REG Node = 'xian:inst6\|d1\[1\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { xian:inst6|d1[1] } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.266 ns) + CELL(0.442 ns) 1.708 ns xian:inst6\|Mux3~62 2 COMB LC_X19_Y12_N0 1 " "Info: 2: + IC(1.266 ns) + CELL(0.442 ns) = 1.708 ns; Loc. = LC_X19_Y12_N0; Fanout = 1; COMB Node = 'xian:inst6\|Mux3~62'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.708 ns" { xian:inst6|d1[1] xian:inst6|Mux3~62 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.114 ns) 2.256 ns xian:inst6\|Mux3~65 3 COMB LC_X19_Y12_N5 7 " "Info: 3: + IC(0.434 ns) + CELL(0.114 ns) = 2.256 ns; Loc. = LC_X19_Y12_N5; Fanout = 7; COMB Node = 'xian:inst6\|Mux3~65'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.548 ns" { xian:inst6|Mux3~62 xian:inst6|Mux3~65 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.442 ns) 3.114 ns xian:inst6\|Mux18~31 4 COMB LC_X19_Y12_N7 1 " "Info: 4: + IC(0.416 ns) + CELL(0.442 ns) = 3.114 ns; Loc. = LC_X19_Y12_N7; Fanout = 1; COMB Node = 'xian:inst6\|Mux18~31'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.858 ns" { xian:inst6|Mux3~65 xian:inst6|Mux18~31 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.410 ns xian:inst6\|data1\[4\] 5 REG LC_X19_Y12_N8 1 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 3.410 ns; Loc. = LC_X19_Y12_N8; Fanout = 1; REG Node = 'xian:inst6\|data1\[4\]'" {  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { xian:inst6|Mux18~31 xian:inst6|data1[4] } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.112 ns ( 32.61 % ) " "Info: Total cell delay = 1.112 ns ( 32.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.298 ns ( 67.39 % ) " "Info: Total interconnect delay = 2.298 ns ( 67.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.410 ns" { xian:inst6|d1[1] xian:inst6|Mux3~62 xian:inst6|Mux3~65 xian:inst6|Mux18~31 xian:inst6|data1[4] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/work/quartusii7