second.tan.qmsg

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -64 -136 32 -48 "clk" "" } } } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "48 " "Warning: Found 48 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux0~48 " "Info: Detected gated clock \"xian:inst6\|Mux0~48\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux0~48" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux0~47 " "Info: Detected gated clock \"xian:inst6\|Mux0~47\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux0~47" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux0~46 " "Info: Detected gated clock \"xian:inst6\|Mux0~46\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux0~46" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux0~45 " "Info: Detected gated clock \"xian:inst6\|Mux0~45\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux0~45" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux0~44 " "Info: Detected gated clock \"xian:inst6\|Mux0~44\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux0~44" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux1~59 " "Info: Detected gated clock \"xian:inst6\|Mux1~59\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux1~59" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux1~58 " "Info: Detected gated clock \"xian:inst6\|Mux1~58\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux1~58" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux1~57 " "Info: Detected gated clock \"xian:inst6\|Mux1~57\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux1~57" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux1~56 " "Info: Detected gated clock \"xian:inst6\|Mux1~56\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux1~56" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux1~55 " "Info: Detected gated clock \"xian:inst6\|Mux1~55\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux1~55" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux2~46 " "Info: Detected gated clock \"xian:inst6\|Mux2~46\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux2~46" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux2~45 " "Info: Detected gated clock \"xian:inst6\|Mux2~45\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux2~45" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux2~44 " "Info: Detected gated clock \"xian:inst6\|Mux2~44\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux2~44" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux2~43 " "Info: Detected gated clock \"xian:inst6\|Mux2~43\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux2~43" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "xian:inst6\|Mux2~42 " "Info: Detected gated clock \"xian:inst6\|Mux2~42\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|Mux2~42" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "xian:inst6\|d1\[1\] " "Info: Detected ripple clock \"xian:inst6\|d1\[1\]\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|d1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "xian:inst6\|d1\[2\] " "Info: Detected ripple clock \"xian:inst6\|d1\[2\]\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|d1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fp2:inst12\|clk1 " "Info: Detected ripple clock \"fp2:inst12\|clk1\" as buffer" {  } { { "fp2.vhd" "" { Text "F:/FPGA_CHENGXU/second/fp2.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "fp2:inst12\|clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "xian:inst6\|d1\[0\] " "Info: Detected ripple clock \"xian:inst6\|d1\[0\]\" as buffer" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "xian:inst6\|d1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst4\|QH\[3\] " "Info: Detected ripple clock \"cnt_60:inst4\|QH\[3\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst4\|QH\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst4\|QH\[2\] " "Info: Detected ripple clock \"cnt_60:inst4\|QH\[2\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst4\|QH\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst4\|QH\[1\] " "Info: Detected ripple clock \"cnt_60:inst4\|QH\[1\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst4\|QH\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst3\|QH\[2\] " "Info: Detected ripple clock \"cnt_60:inst3\|QH\[2\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QH\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst3\|QH\[3\] " "Info: Detected ripple clock \"cnt_60:inst3\|QH\[3\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QH\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst3\|QH\[1\] " "Info: Detected ripple clock \"cnt_60:inst3\|QH\[1\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QH\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_12:inst5\|QH\[3\] " "Info: Detected ripple clock \"cnt_12:inst5\|QH\[3\]\" as buffer" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_12:inst5\|QH\[1\] " "Info: Detected ripple clock \"cnt_12:inst5\|QH\[1\]\" as buffer" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_12:inst5\|QH\[2\] " "Info: Detected ripple clock \"cnt_12:inst5\|QH\[2\]\" as buffer" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_12:inst5\|QL\[2\] " "Info: Detected ripple clock \"cnt_12:inst5\|QL\[2\]\" as buffer" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QL\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_12:inst5\|QL\[3\] " "Info: Detected ripple clock \"cnt_12:inst5\|QL\[3\]\" as buffer" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QL\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_12:inst5\|QL\[1\] " "Info: Detected ripple clock \"cnt_12:inst5\|QL\[1\]\" as buffer" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QL\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_10:inst1\|Q\[3\] " "Info: Detected ripple clock \"cnt_10:inst1\|Q\[3\]\" as buffer" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_10:inst1\|Q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_10:inst1\|Q\[2\] " "Info: Detected ripple clock \"cnt_10:inst1\|Q\[2\]\" as buffer" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_10:inst1\|Q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_10:inst1\|Q\[1\] " "Info: Detected ripple clock \"cnt_10:inst1\|Q\[1\]\" as buffer" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_10:inst1\|Q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_10:inst2\|Q\[1\] " "Info: Detected ripple clock \"cnt_10:inst2\|Q\[1\]\" as buffer" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_10:inst2\|Q\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_10:inst2\|Q\[3\] " "Info: Detected ripple clock \"cnt_10:inst2\|Q\[3\]\" as buffer" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_10:inst2\|Q\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_10:inst2\|Q\[2\] " "Info: Detected ripple clock \"cnt_10:inst2\|Q\[2\]\" as buffer" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_10:inst2\|Q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst3\|QL\[2\] " "Info: Detected ripple clock \"cnt_60:inst3\|QL\[2\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QL\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst3\|QL\[3\] " "Info: Detected ripple clock \"cnt_60:inst3\|QL\[3\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QL\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst3\|QL\[1\] " "Info: Detected ripple clock \"cnt_60:inst3\|QL\[1\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QL\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst4\|QL\[2\] " "Info: Detected ripple clock \"cnt_60:inst4\|QL\[2\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst4\|QL\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst4\|QL\[3\] " "Info: Detected ripple clock \"cnt_60:inst4\|QL\[3\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst4\|QL\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst4\|QL\[1\] " "Info: Detected ripple clock \"cnt_60:inst4\|QL\[1\]\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst4\|QL\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_10:inst1\|co " "Info: Detected ripple clock \"cnt_10:inst1\|co\" as buffer" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_10:inst1\|co" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst\|clk1 " "Info: Detected ripple clock \"fenpin:inst\|clk1\" as buffer" {  } { { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 20 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpin:inst\|clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst4\|co " "Info: Detected ripple clock \"cnt_60:inst4\|co\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst4\|co" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_10:inst2\|co " "Info: Detected ripple clock \"cnt_10:inst2\|co\" as buffer" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_10:inst2\|co" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cnt_60:inst3\|co " "Info: Detected ripple clock \"cnt_60:inst3\|co\" as buffer" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|co" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}