prev_cmp_second.qmsg

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

{ "Info" "IMPP_MPP_USER_DEVICE" "second EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"second\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "209 Top " "Info: Previous placement does not exist for 209 of 209 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 12 " "Info: Pin ~nCSO~ is reserved at location 12" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 25 " "Info: Pin ~ASDO~ is reserved at location 25" {  } { { "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/work/quartusii7.2/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 93 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 93" {  } { { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -64 -136 32 -48 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt_10:inst2\|co Global clock " "Info: Automatically promoted some destinations of signal \"cnt_10:inst2\|co\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt_10:inst2\|co " "Info: Destination \"cnt_10:inst2\|co\" may be non-global or may not use global clock" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt_60:inst3\|co Global clock " "Info: Automatically promoted some destinations of signal \"cnt_60:inst3\|co\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt_60:inst3\|co " "Info: Destination \"cnt_60:inst3\|co\" may be non-global or may not use global clock" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt_60:inst4\|co Global clock " "Info: Automatically promoted some destinations of signal \"cnt_60:inst4\|co\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt_60:inst4\|co " "Info: Destination \"cnt_60:inst4\|co\" may be non-global or may not use global clock" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "xian:inst6\|Mux22~55 Global clock " "Info: Automatically promoted signal \"xian:inst6\|Mux22~55\" to use Global clock" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 38 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt_10:inst1\|co Global clock " "Info: Automatically promoted some destinations of signal \"cnt_10:inst1\|co\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt_10:inst1\|co " "Info: Destination \"cnt_10:inst1\|co\" may be non-global or may not use global clock" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fenpin:inst\|clk1 Global clock " "Info: Automatically promoted signal \"fenpin:inst\|clk1\" to use Global clock" {  } { { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 20 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fp2:inst12\|clk1 Global clock " "Info: Automatically promoted signal \"fp2:inst12\|clk1\" to use Global clock" {  } { { "fp2.vhd" "" { Text "F:/FPGA_CHENGXU/second/fp2.vhd" 17 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}