prev_cmp_second.fit.qmsg

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 93 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 93" {  } { { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -64 -136 32 -48 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt_10:inst2\|co Global clock " "Info: Automatically promoted some destinations of signal \"cnt_10:inst2\|co\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt_10:inst2\|co " "Info: Destination \"cnt_10:inst2\|co\" may be non-global or may not use global clock" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt_60:inst3\|co Global clock " "Info: Automatically promoted some destinations of signal \"cnt_60:inst3\|co\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt_60:inst3\|co " "Info: Destination \"cnt_60:inst3\|co\" may be non-global or may not use global clock" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt_60:inst4\|co Global clock " "Info: Automatically promoted some destinations of signal \"cnt_60:inst4\|co\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt_60:inst4\|co " "Info: Destination \"cnt_60:inst4\|co\" may be non-global or may not use global clock" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "xian:inst6\|Mux22~55 Global clock " "Info: Automatically promoted signal \"xian:inst6\|Mux22~55\" to use Global clock" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 38 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cnt_10:inst1\|co Global clock " "Info: Automatically promoted some destinations of signal \"cnt_10:inst1\|co\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cnt_10:inst1\|co " "Info: Destination \"cnt_10:inst1\|co\" may be non-global or may not use global clock" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fenpin:inst\|clk1 Global clock " "Info: Automatically promoted signal \"fenpin:inst\|clk1\" to use Global clock" {  } { { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 20 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fp2:inst12\|clk1 Global clock " "Info: Automatically promoted signal \"fp2:inst12\|clk1\" to use Global clock" {  } { { "fp2.vhd" "" { Text "F:/FPGA_CHENGXU/second/fp2.vhd" 17 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}