second.map.qmsg

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data1 xian.vhd(71) " "Warning (10492): VHDL Process Statement warning at xian.vhd(71): signal \"data1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 71 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "data1 xian.vhd(22) " "Warning (10631): VHDL Process Statement warning at xian.vhd(22): inferring latch(es) for signal or variable \"data1\", which holds its previous value in one or more paths through the process" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data1\[0\] xian.vhd(22) " "Info (10041): Inferred latch for \"data1\[0\]\" at xian.vhd(22)" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data1\[1\] xian.vhd(22) " "Info (10041): Inferred latch for \"data1\[1\]\" at xian.vhd(22)" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data1\[2\] xian.vhd(22) " "Info (10041): Inferred latch for \"data1\[2\]\" at xian.vhd(22)" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data1\[3\] xian.vhd(22) " "Info (10041): Inferred latch for \"data1\[3\]\" at xian.vhd(22)" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data1\[4\] xian.vhd(22) " "Info (10041): Inferred latch for \"data1\[4\]\" at xian.vhd(22)" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data1\[5\] xian.vhd(22) " "Info (10041): Inferred latch for \"data1\[5\]\" at xian.vhd(22)" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data1\[6\] xian.vhd(22) " "Info (10041): Inferred latch for \"data1\[6\]\" at xian.vhd(22)" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "data1\[7\] xian.vhd(22) " "Info (10041): Inferred latch for \"data1\[7\]\" at xian.vhd(22)" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp2 fp2:inst12 " "Info: Elaborating entity \"fp2\" for hierarchy \"fp2:inst12\"" {  } { { "second.bdf" "inst12" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { 216 88 184 312 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt_12 cnt_12:inst5 " "Info: Elaborating entity \"cnt_12\" for hierarchy \"cnt_12:inst5\"" {  } { { "second.bdf" "inst5" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -88 1176 1296 8 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt_60 cnt_60:inst4 " "Info: Elaborating entity \"cnt_60\" for hierarchy \"cnt_60:inst4\"" {  } { { "second.bdf" "inst4" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -88 936 1056 8 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt_10 cnt_10:inst2 " "Info: Elaborating entity \"cnt_10\" for hierarchy \"cnt_10:inst2\"" {  } { { "second.bdf" "inst2" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -88 480 592 8 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenpin fenpin:inst " "Info: Elaborating entity \"fenpin\" for hierarchy \"fenpin:inst\"" {  } { { "second.bdf" "inst" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { -88 72 168 8 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "start fenpin.vhd(19) " "Warning (10492): VHDL Process Statement warning at fenpin.vhd(19): signal \"start\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "ddd~0 " "Warning: Replaced VCC or GND feeding tri-state bus ddd~0 with an always-enabled tri-state buffer" {  } { { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { 352 -64 112 368 "ddd" "" } } } }  } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "xian:inst6\|data1\[7\] " "Warning: Latch xian:inst6\|data1\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA xian:inst6\|d1\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6\|d1\[0\]" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "xian:inst6\|data1\[6\] " "Warning: Latch xian:inst6\|data1\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA xian:inst6\|d1\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6\|d1\[0\]" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "xian:inst6\|data1\[5\] " "Warning: Latch xian:inst6\|data1\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA xian:inst6\|d1\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6\|d1\[0\]" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "xian:inst6\|data1\[4\] " "Warning: Latch xian:inst6\|data1\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA xian:inst6\|d1\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6\|d1\[0\]" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "xian:inst6\|data1\[3\] " "Warning: Latch xian:inst6\|data1\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA xian:inst6\|d1\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6\|d1\[0\]" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "xian:inst6\|data1\[2\] " "Warning: Latch xian:inst6\|data1\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA xian:inst6\|d1\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6\|d1\[0\]" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "xian:inst6\|data1\[1\] " "Warning: Latch xian:inst6\|data1\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA xian:inst6\|d1\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6\|d1\[0\]" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 74 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "209 " "Info: Implemented 209 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "188 " "Info: Implemented 188 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 34 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 07 18:30:00 2008 " "Info: Processing ended: Tue Oct 07 18:30:00 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}