📄 add.tan.qmsg

📁 vhdl的最简单的加法器
💻 QMSG
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{ "Info" "ITAN_NO_REG2REG_EXIST" "clki " "Info: No valid register-to-register data paths exist for clock \"clki\"" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "o~reg0 enable clki 1.600 ns register " "Info: tsu for register \"o~reg0\" (data pin = \"enable\", clock pin = \"clki\") is 1.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.400 ns + Longest pin register " "Info: + Longest pin to register delay is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns enable 1 PIN PIN_126 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 1; PIN Node = 'enable'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "" { enable } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(1.000 ns) 3.400 ns o~reg0 2 REG LC4_C27 1 " "Info: 2: + IC(0.400 ns) + CELL(1.000 ns) = 3.400 ns; Loc. = LC4_C27; Fanout = 1; REG Node = 'o~reg0'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "1.400 ns" { enable o~reg0 } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 88.24 % " "Info: Total cell delay = 3.000 ns ( 88.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 11.76 % " "Info: Total interconnect delay = 0.400 ns ( 11.76 % )" {  } {  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "3.400 ns" { enable o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { enable enable~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clki destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clki\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clki 1 CLK PIN_55 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 1; CLK Node = 'clki'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "" { clki } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns o~reg0 2 REG LC4_C27 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_C27; Fanout = 1; REG Node = 'o~reg0'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "0.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "2.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clki clki~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "3.400 ns" { enable o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { enable enable~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 1.000ns } } } { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "2.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clki clki~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clki o o~reg0 10.500 ns register " "Info: tco from clock \"clki\" to destination pin \"o\" through register \"o~reg0\" is 10.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clki source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clki\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clki 1 CLK PIN_55 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 1; CLK Node = 'clki'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "" { clki } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns o~reg0 2 REG LC4_C27 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_C27; Fanout = 1; REG Node = 'o~reg0'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "0.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "2.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clki clki~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register pin " "Info: + Longest register to pin delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns o~reg0 1 REG LC4_C27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C27; Fanout = 1; REG Node = 'o~reg0'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "" { o~reg0 } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(6.300 ns) 7.600 ns o 2 PIN PIN_14 0 " "Info: 2: + IC(1.300 ns) + CELL(6.300 ns) = 7.600 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'o'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "7.600 ns" { o~reg0 o } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 82.89 % " "Info: Total cell delay = 6.300 ns ( 82.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns 17.11 % " "Info: Total interconnect delay = 1.300 ns ( 17.11 % )" {  } {  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "7.600 ns" { o~reg0 o } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.600 ns" { o~reg0 o } { 0.000ns 1.300ns } { 0.000ns 6.300ns } } }  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "2.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clki clki~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "7.600 ns" { o~reg0 o } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.600 ns" { o~reg0 o } { 0.000ns 1.300ns } { 0.000ns 6.300ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "o~reg0 i2 clki 0.500 ns register " "Info: th for register \"o~reg0\" (data pin = \"i2\", clock pin = \"clki\") is 0.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clki destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clki\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clki 1 CLK PIN_55 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 1; CLK Node = 'clki'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "" { clki } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns o~reg0 2 REG LC4_C27 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_C27; Fanout = 1; REG Node = 'o~reg0'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "0.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "2.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clki clki~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns i2 1 PIN PIN_54 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 1; PIN Node = 'i2'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "" { i2 } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.800 ns) 3.200 ns o~reg0 2 REG LC4_C27 1 " "Info: 2: + IC(0.400 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC4_C27; Fanout = 1; REG Node = 'o~reg0'" {  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "1.200 ns" { i2 o~reg0 } "NODE_NAME" } "" } } { "add.vhd" "" { Text "D:/1/add/add.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 87.50 % " "Info: Total cell delay = 2.800 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 12.50 % " "Info: Total interconnect delay = 0.400 ns ( 12.50 % )" {  } {  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "3.200 ns" { i2 o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { i2 i2~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.800ns } } }  } 0}  } { { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "2.400 ns" { clki o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clki clki~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/1/add/db/add_cmp.qrpt" "" { Report "D:/1/add/db/add_cmp.qrpt" Compiler "add" "UNKNOWN" "V1" "D:/1/add/db/add.quartus_db" { Floorplan "D:/1/add/" "" "3.200 ns" { i2 o~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { i2 i2~out o~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 25 15:13:23 2008 " "Info: Processing ended: Thu Dec 25 15:13:23 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
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