add.vhd

来自「vhdl的最简单的加法器」· VHDL 代码 · 共 25 行

library ieee;   
 use ieee.std_logic_1164.all;  
 use ieee.std_logic_unsigned.all;   
  
 entity add is   
     port   
     (      
           
         i1,i2,enable,clki  :in  std_logic;   
         o :out std_logic);  
 end add;   
    
 architecture behave_add of add is   
  begin
process(clki)
begin
if(clki'event and clki='1')then   
if enable='1' then
o<=i1 xor i2;
 else
o<='0';
end if;
end if;
end process;
end behave_add;