add.fit.eqn

vhdl的最简单的加法器

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--A1L7Q is o~reg0 at LC4_C27
--operation mode is normal

A1L7Q_lut_out = enable & (i1 $ i2);
A1L7Q = DFFEA(A1L7Q_lut_out, GLOBAL(clki), , , , , );

--A1L6Q is o~11 at LC4_C27
--operation mode is normal

A1L6Q = A1L7Q;


--enable is enable at PIN_126
--operation mode is input

enable = INPUT();


--i1 is i1 at PIN_124
--operation mode is input

i1 = INPUT();


--i2 is i2 at PIN_54
--operation mode is input

i2 = INPUT();


--clki is clki at PIN_55
--operation mode is input

clki = INPUT();


--o is o at PIN_14
--operation mode is output

o = OUTPUT(A1L7Q);