ctrl.map.summary

quarters2编写的定时器.vhd为源程序

Flow Status : Successful - Wed Dec 24 23:09:02 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : ctrl
Top-level Entity Name : ctrl
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 38
Total pins : 12
Total memory bits : 0
Total PLLs : 0