shifter.map.qmsg

使用QUARTUS2写的循环码编码器源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 30 14:15:31 2008 " "Info: Processing started: Tue Dec 30 14:15:31 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off shifter -c shifter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shifter -c shifter" {  } {  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "output0 shifter.vhd(15) " "Error: VHDL error at shifter.vhd(15): object \"output0\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 15 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d3 shifter.vhd(16) " "Error: VHDL error at shifter.vhd(16): object \"d3\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 16 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "output0 shifter.vhd(16) " "Error: VHDL error at shifter.vhd(16): object \"output0\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 16 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d3 shifter.vhd(17) " "Error: VHDL error at shifter.vhd(17): object \"d3\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 17 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d1 shifter.vhd(18) " "Error: VHDL error at shifter.vhd(18): object \"d1\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 18 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d0 shifter.vhd(19) " "Error: VHDL error at shifter.vhd(19): object \"d0\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 19 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "output1 shifter.vhd(20) " "Error: VHDL error at shifter.vhd(20): object \"output1\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 20 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d3 shifter.vhd(21) " "Error: VHDL error at shifter.vhd(21): object \"d3\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 21 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "output1 shifter.vhd(21) " "Error: VHDL error at shifter.vhd(21): object \"output1\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 21 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d3 shifter.vhd(22) " "Error: VHDL error at shifter.vhd(22): object \"d3\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 22 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d1 shifter.vhd(23) " "Error: VHDL error at shifter.vhd(23): object \"d1\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 23 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d0 shifter.vhd(24) " "Error: VHDL error at shifter.vhd(24): object \"d0\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 24 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "output2 shifter.vhd(25) " "Error: VHDL error at shifter.vhd(25): object \"output2\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 25 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d3 shifter.vhd(26) " "Error: VHDL error at shifter.vhd(26): object \"d3\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 26 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "output2 shifter.vhd(26) " "Error: VHDL error at shifter.vhd(26): object \"output2\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 26 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d3 shifter.vhd(27) " "Error: VHDL error at shifter.vhd(27): object \"d3\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 27 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d1 shifter.vhd(28) " "Error: VHDL error at shifter.vhd(28): object \"d1\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 28 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "d0 shifter.vhd(29) " "Error: VHDL error at shifter.vhd(29): object \"d0\" is used but not declared" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 29 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_NO_UNIQUE_OPER_DEFN_MATCH" "0 \"<=\" shifter.vhd(32) " "Error: VHDL error at shifter.vhd(32): can't determine definition of operator \"\"<=\"\" -- found 0 possible definitions" {  } { { "shifter.vhd" "" { Text "D:/1/bianma/shifter.vhd" 32 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file shifter.vhd" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 19 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Dec 30 14:15:32 2008 " "Error: Processing ended: Tue Dec 30 14:15:32 2008" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}