clk_div.vhd

来自「介绍了各种分频器的设计」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
	port(clk:in std_logic;
		clk_div2:out std_logic;
		clk_div4:out std_logic;
		clk_div8:out std_logic);
end clk_div;
ARCHITECTURE a OF clk_div IS
	SIGNAL count:std_logic_vector(2 downto 0);
BEGIN
	process(clk)
	begin
		if clk'event and clk='1' then 
			if count="111" then
				count<=(others=>'0');
			else
				count<=count+1;
			end if;
		end if;
	end process;
	clk_div2<=not count(0);
	clk_div4<=not count(1);
	clk_div8<=not count(2);
END a;