clk_div.fit

介绍了各种分频器的设计

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 03/29/2009 16:00:16      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "clk_div"
BEGIN

    DEVICE = "EPF10K30ETC144-1";

    "clk"                          : INPUT_PIN  = 55     ;
    "clk_div2"                     : OUTPUT_PIN = 60     ;
    "clk_div4"                     : OUTPUT_PIN = 98     ;
    "clk_div8"                     : OUTPUT_PIN = 9      ;
    ":5"                           : LOCATION   = LC2_B16;  -- count2
    ":6"                           : LOCATION   = LC5_B16;  -- count1
    ":7"                           : LOCATION   = LC6_B16;  -- count0

END;

INTERNAL_INFO "clk_div"
BEGIN
	DEVICE = EPF10K30ETC144-1;
    OD5P55  : LORAX = "1:FB5->LC2_B16,->LC5_B16,->LC6_B16|";
    LC2_B16 : LORAX = "1:MSW2R1C14,G51R1->OH2R1P9|";
    LC5_B16 : LORAX = "1:MSW5R1C14,HHL69R1->OH13R1P98|";
    LC6_B16 : LORAX = "1:MSW6R1C14,V20C14->OV3C14P60|";
	LC2_B16 : LORAX2 = "X, LC2_B16, LC5_B16, LC6_B16";
	LC5_B16 : LORAX2 = "X, X, LC5_B16, LC6_B16";
	LC6_B16 : LORAX2 = "X, X, X, LC6_B16";
END;