clk_div.vhd

来自「介绍了各种分频器的设计」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
	port(clk:in std_logic;
		clk_div10:out std_logic);
end clk_div;
ARCHITECTURE a OF clk_div IS
	SIGNAL count : STD_LOGIC_vector(2 downto 0);
	SIGNAL clk_tmp: STD_LOGIC;
BEGIN
	process(clk)
		constant md:std_logic_vector(2 downto 0):="100";
	begin
		if clk'event and clk='1' then
			if count=md then
				count<=(others=>'0');
				clk_tmp<=not clk_tmp;
			else
				count<=count+1;
			end if;
		end if;
	end process;
	clk_div10<=clk_tmp;

END a;