clk_div.vhd

来自「介绍了各种分频器的设计」· VHDL 代码 · 共 43 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
	port(clk 		:	in std_logic;		 
		 clk_out	:	out std_logic);
end clk_div;

ARCHITECTURE a OF clk_div IS
	constant md:std_logic_vector(3 downto 0):="0011";
	signal count :	std_logic_vector(3 downto 0);
	signal clk_tmp1:std_logic;
	signal clk_tmp2:std_logic;
	signal clk_out_tmp:std_logic;
BEGIN
	clk_tmp1<=clk xor clk_tmp2;
	modn_counter:process(clk_tmp1)
	begin
		if clk_tmp1'event and clk_tmp1='1' then
			if count="0000" then 
				count<=md-1;
				clk_out<='1';
				clk_out_tmp<='1';
			else
				count<=count-1;
				clk_out<='0';
				clk_out_tmp<='0';
			end if;
		end if;
	end process modn_counter;
	
	half_clk:process(clk_out_tmp)
	begin
		if clk_out_tmp'event and clk_out_tmp='1' then
			clk_tmp2<=not clk_tmp2;
		end if;
	end process half_clk;

END a;