clk_div.fit

介绍了各种分频器的设计

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 03/29/2009 18:16:24      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "clk_div"
BEGIN

    DEVICE = "EPF10K30ETC144-1";

    "clk"                          : INPUT_PIN  = 54     ;
    "clk_out"                      : OUTPUT_PIN = 23     ;
    ":2"                           : LOCATION   = LC7_D25;
    ":5"                           : LOCATION   = LC8_D25;  -- count3
    ":6"                           : LOCATION   = LC6_D25;  -- count2
    ":7"                           : LOCATION   = LC4_D25;  -- count1
    ":8"                           : LOCATION   = LC5_D25;  -- count0
    ":9"                           : LOCATION   = LC1_D25;  -- clk_out_tmp
    ":10"                          : LOCATION   = LC1_D21;  -- clk_tmp2
    ":32"                          : LOCATION   = LC3_D25;
    ":200"                         : LOCATION   = LC2_D25;

END;

INTERNAL_INFO "clk_div"
BEGIN
	DEVICE = EPF10K30ETC144-1;
    OD2P54  : LORAX = "1:FB2|2:FH2R3,PA6R3C24->LC2_D25||";
    LC7_D25 : LORAX = "1:MSW6R3C24,G128R3->OH6R3P23|";
    LC1_D25 : LORAX = "1:MSW0R3C24,HHR34R3,PA7R3C20->LC1_D21|";
    LC1_D21 : LORAX = "1:MSW0R3C20,HHR30R3,PA8R3C24->LC2_D25|";
	LC7_D25 : LORAX2 = "LC8_D25, LC6_D25, LC4_D25, LC5_D25";
	LC8_D25 : LORAX2 = "LC8_D25, LC6_D25, LC4_D25, LC5_D25";
	LC6_D25 : LORAX2 = "LC6_D25, LC8_D25, LC4_D25, LC5_D25";
	LC4_D25 : LORAX2 = "X, LC3_D25, LC4_D25, LC5_D25";
	LC5_D25 : LORAX2 = "LC8_D25, LC4_D25, LC6_D25, LC5_D25";
	LC1_D25 : LORAX2 = "LC8_D25, LC6_D25, LC4_D25, LC5_D25";
	LC1_D21 : LORAX2 = "X, X, X, LC1_D21";
	LC3_D25 : LORAX2 = "LC8_D25, LC6_D25, LC4_D25, LC5_D25";
	LC2_D25 : LORAX2 = "X, X, OD2P54, LC1_D21";
END;