📄 clk_div.rpt
字号:
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\my work bench\vhdl\resource\fenping\2.5div\clk_div.rpt
clk_div
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - D 25 DFFE 0 5 1 0 :2
- 8 - D 25 DFFE 0 4 0 5 count3 (:5)
- 6 - D 25 DFFE 0 4 0 5 count2 (:6)
- 4 - D 25 DFFE 0 3 0 6 count1 (:7)
- 5 - D 25 DFFE 0 4 0 6 count0 (:8)
- 1 - D 25 DFFE 0 5 0 1 clk_out_tmp (:9)
- 1 - D 21 DFFE 0 1 0 1 clk_tmp2 (:10)
- 3 - D 25 AND2 0 4 0 1 :32
- 2 - D 25 OR2 1 1 0 6 :200
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:e:\my work bench\vhdl\resource\fenping\2.5div\clk_div.rpt
clk_div
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 1/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\my work bench\vhdl\resource\fenping\2.5div\clk_div.rpt
clk_div
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 6 :200
DFF 1 clk_out_tmp
Device-Specific Information:e:\my work bench\vhdl\resource\fenping\2.5div\clk_div.rpt
clk_div
** EQUATIONS **
clk : INPUT;
-- Node name is 'clk_out'
-- Equation name is 'clk_out', type is output
clk_out = _LC7_D25;
-- Node name is ':9' = 'clk_out_tmp'
-- Equation name is 'clk_out_tmp', location is LC1_D25, type is buried.
clk_out_tmp = DFFE( _EQ001, _LC2_D25, VCC, VCC, VCC);
_EQ001 = !count0 & !count1 & !count2 & !count3;
-- Node name is ':10' = 'clk_tmp2'
-- Equation name is 'clk_tmp2', location is LC1_D21, type is buried.
clk_tmp2 = DFFE(!clk_tmp2, clk_out_tmp, VCC, VCC, VCC);
-- Node name is ':8' = 'count0'
-- Equation name is 'count0', location is LC5_D25, type is buried.
count0 = DFFE( _EQ002, _LC2_D25, VCC, VCC, VCC);
_EQ002 = !count0 & count3
# !count0 & count2
# !count0 & count1;
-- Node name is ':7' = 'count1'
-- Equation name is 'count1', location is LC4_D25, type is buried.
count1 = DFFE( _EQ003, _LC2_D25, VCC, VCC, VCC);
_EQ003 = _LC3_D25
# count0 & count1
# !count0 & !count1;
-- Node name is ':6' = 'count2'
-- Equation name is 'count2', location is LC6_D25, type is buried.
count2 = DFFE( _EQ004, _LC2_D25, VCC, VCC, VCC);
_EQ004 = count0 & count2
# count1 & count2
# !count0 & !count1 & !count2 & count3;
-- Node name is ':5' = 'count3'
-- Equation name is 'count3', location is LC8_D25, type is buried.
count3 = DFFE( _EQ005, _LC2_D25, VCC, VCC, VCC);
_EQ005 = count0 & count3
# count1 & count3
# count2 & count3;
-- Node name is ':2'
-- Equation name is '_LC7_D25', type is buried
_LC7_D25 = DFFE( _EQ006, _LC2_D25, VCC, VCC, VCC);
_EQ006 = !count0 & !count1 & !count2 & !count3;
-- Node name is ':32'
-- Equation name is '_LC3_D25', type is buried
_LC3_D25 = LCELL( _EQ007);
_EQ007 = !count0 & !count1 & !count2 & !count3;
-- Node name is ':200'
-- Equation name is '_LC2_D25', type is buried
_LC2_D25 = LCELL( _EQ008);
_EQ008 = !clk & clk_tmp2
# clk & !clk_tmp2;
Project Information e:\my work bench\vhdl\resource\fenping\2.5div\clk_div.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10KE' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:04
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 51,956K
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