clk_div.fit

介绍了各种分频器的设计

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 03/29/2009 17:28:57      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "clk_div"
BEGIN

    DEVICE = "EPF10K30ETC144-1";

    "clk"                          : INPUT_PIN  = 55     ;
    "clk_div5"                     : OUTPUT_PIN = 78     ;
    "flag1"                        : OUTPUT_PIN = 79     ;
    "flag2"                        : OUTPUT_PIN = 81     ;
    ":5"                           : LOCATION   = LC7_F4 ;  -- countr2
    ":6"                           : LOCATION   = LC8_F3 ;  -- countr1
    ":7"                           : LOCATION   = LC5_F4 ;  -- countr0
    ":8"                           : LOCATION   = LC4_F4 ;  -- countf2
    ":9"                           : LOCATION   = LC3_F4 ;  -- countf1
    ":10"                          : LOCATION   = LC1_F4 ;  -- countf0
    ":11"                          : LOCATION   = LC6_F4 ;  -- levelr
    ":12"                          : LOCATION   = LC2_F4 ;  -- levelf
    ":338"                         : LOCATION   = LC8_F4 ;

END;

INTERNAL_INFO "clk_div"
BEGIN
	DEVICE = EPF10K30ETC144-1;
    OD5P55  : LORAX = "1:FB5->LC7_F4,->LC8_F3,->LC5_F4,->LC4_F4,->LC3_F4,->LC1_F4,->LC6_F4,->LC2_F4|";
    LC8_F3  : LORAX = "1:MSW7R5C2,G100R5,PA0R5C3->LC7_F4,->LC5_F4,->LC6_F4|";
    LC5_F4  : LORAX = "1:MSW5R5C2,G138R5,PA10R5C2->LC8_F3|";
    LC6_F4  : LORAX = "1:MSW5R5C3,HHL40R5->OH13R5P79|";
    LC2_F4  : LORAX = "1:MSW1R5C3,G33R5->OH9R5P81|";
    LC8_F4  : LORAX = "1:MSW7R5C3,HHL41R5->OH15R5P78|";
	LC7_F4  : LORAX2 = "X, LC8_F3, LC5_F4, LC7_F4";
	LC8_F3  : LORAX2 = "X, X, LC8_F3, LC5_F4";
	LC5_F4  : LORAX2 = "X, LC8_F3, LC5_F4, LC7_F4";
	LC4_F4  : LORAX2 = "X, LC3_F4, LC1_F4, LC4_F4";
	LC3_F4  : LORAX2 = "X, X, LC3_F4, LC1_F4";
	LC1_F4  : LORAX2 = "X, LC3_F4, LC1_F4, LC4_F4";
	LC6_F4  : LORAX2 = "LC7_F4, LC8_F3, LC5_F4, LC6_F4";
	LC2_F4  : LORAX2 = "LC4_F4, LC3_F4, LC1_F4, LC2_F4";
	LC8_F4  : LORAX2 = "X, X, LC2_F4, LC6_F4";
END;