📄 clk_div.rpt
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Device-Specific Information:e:\my work bench\vhdl\resource\fenping\zhangdongjishu\clk_div.rpt
clk_div
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - F 04 DFFE + 0 2 0 2 countr2 (:5)
- 8 - F 03 DFFE + 0 1 0 3 countr1 (:6)
- 5 - F 04 DFFE + 0 2 0 3 countr0 (:7)
- 4 - F 04 DFFE + 0 2 0 2 countf2 (:8)
- 3 - F 04 DFFE + 0 1 0 3 countf1 (:9)
- 1 - F 04 DFFE + 0 2 0 3 countf0 (:10)
- 6 - F 04 DFFE + 0 3 1 1 levelr (:11)
- 2 - F 04 DFFE + 0 3 1 1 levelf (:12)
- 8 - F 04 OR2 0 2 1 0 :338
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:e:\my work bench\vhdl\resource\fenping\zhangdongjishu\clk_div.rpt
clk_div
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 3/144( 2%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\my work bench\vhdl\resource\fenping\zhangdongjishu\clk_div.rpt
clk_div
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information:e:\my work bench\vhdl\resource\fenping\zhangdongjishu\clk_div.rpt
clk_div
** EQUATIONS **
clk : INPUT;
-- Node name is 'clk_div5'
-- Equation name is 'clk_div5', type is output
clk_div5 = _LC8_F4;
-- Node name is ':10' = 'countf0'
-- Equation name is 'countf0', location is LC1_F4, type is buried.
countf0 = DFFE( _EQ001, GLOBAL(!clk), VCC, VCC, VCC);
_EQ001 = !countf0 & !countf2
# !countf0 & countf1;
-- Node name is ':9' = 'countf1'
-- Equation name is 'countf1', location is LC3_F4, type is buried.
countf1 = DFFE( _EQ002, GLOBAL(!clk), VCC, VCC, VCC);
_EQ002 = countf0 & !countf1
# !countf0 & countf1;
-- Node name is ':8' = 'countf2'
-- Equation name is 'countf2', location is LC4_F4, type is buried.
countf2 = DFFE( _EQ003, GLOBAL(!clk), VCC, VCC, VCC);
_EQ003 = countf0 & countf1 & !countf2
# !countf0 & countf1 & countf2
# countf0 & !countf1 & countf2;
-- Node name is ':7' = 'countr0'
-- Equation name is 'countr0', location is LC5_F4, type is buried.
countr0 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !countr0 & !countr2
# !countr0 & countr1;
-- Node name is ':6' = 'countr1'
-- Equation name is 'countr1', location is LC8_F3, type is buried.
countr1 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = countr0 & !countr1
# !countr0 & countr1;
-- Node name is ':5' = 'countr2'
-- Equation name is 'countr2', location is LC7_F4, type is buried.
countr2 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = countr0 & countr1 & !countr2
# !countr0 & countr1 & countr2
# countr0 & !countr1 & countr2;
-- Node name is 'flag1'
-- Equation name is 'flag1', type is output
flag1 = levelr;
-- Node name is 'flag2'
-- Equation name is 'flag2', type is output
flag2 = levelf;
-- Node name is ':12' = 'levelf'
-- Equation name is 'levelf', location is LC2_F4, type is buried.
levelf = DFFE( _EQ007, GLOBAL(!clk), VCC, VCC, VCC);
_EQ007 = !countf0 & !countf1 & !countf2
# countf0 & levelf
# !countf1 & levelf
# countf2 & levelf;
-- Node name is ':11' = 'levelr'
-- Equation name is 'levelr', location is LC6_F4, type is buried.
levelr = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !countr0 & !countr1 & !countr2
# countr0 & levelr
# !countr1 & levelr
# countr2 & levelr;
-- Node name is ':338'
-- Equation name is '_LC8_F4', type is buried
_LC8_F4 = LCELL( _EQ009);
_EQ009 = levelr
# levelf;
Project Informatione:\my work bench\vhdl\resource\fenping\zhangdongjishu\clk_div.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10KE' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 50,966K
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