1234.txt

一段NOR FLASH 控制器的Verilog源码

                        endcase

                if (WRITE1 | WRITE2)
                        case (wr_state)
                        0: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        adr =   (wcnt == 0) ? 19'h00555 :
                                                    (wcnt == 1) ? 19'h002AA :
                                                    (wcnt == 2) ? 19'h00555 :
                                                    (wcnt == 3) ? wr_word_adr : 19'hXXXXX;
                                        otkl <= 1;
                                        wr_state = wr_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        1: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        t_we_b = 0;
                                        t_flash_ce_b = 0;
                                        otkl <= 0;
                                        data =  (wcnt == 0) ? 16'h00AA :
                                                    (wcnt == 1) ? 16'h0055 :
                                                            (wcnt == 2) ? 16'h00A0 :
                                                            (wcnt == 3) ? wr_word_data : 16'hXXXX;
                                        wr_state = wr_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        2: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        wr_state = wr_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        3: begin
                                t_we_b = 1;
                                t_flash_ce_b = 1;
                                wcnt = wcnt + 1'b1;
                                if (wcnt < 4) wr_state = 0;
                                else wr_state = wr_state + 1'b1;
                        end
                        4: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        otkl <= 1;//data = 16'hZZZZ;
                                        wcnt = 0;
                                        wr_state = wr_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        5: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        t_oe_b = 0;
                                        t_flash_ce_b = 0;
                                        adr = wr_word_adr;
                                        wr_state = wr_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        6: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        wr_state = wr_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        7: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        delay = 0;
                                        polling_data <= d;
                                        wr_state = wr_state + 1'b1;
                                end
                        end
                        8: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        t_oe_b <= 1;
                                        t_flash_ce_b <= 1;
                                        wr_state = wr_state + 1'b1;
                                        delay = 0;
                                end
                        end
                        9: begin
                                        if (polling_data == wr_word_data) begin
                                                wr_state = wr_state + 1'b1;
                                                wr_errors = 0;
                                        end
                                        else begin
                                                if (wr_errors > 20) begin
                                                        wr_state = wr_state + 1'b1;
                                                        wr_errors = 0;
                                                        err_cnt <= err_cnt + 1'b1;
                                                end
                                                else
                                                        if (polling_data[5] == 1) begin
                                                                wr_errors = wr_errors + 1'b1;
                                                                wr_state = 0;
                                                        end
                                                        else wr_state = 5;
                                        end
                        end
                        10: begin
                                delay = delay + 1'b1;
                                if (delay == 10) begin
                                        if (WRITE1) {stop_writing_1, wr_word_adr} <= wr_word_adr + 1;
                                        else if (WRITE2) {stop_writing_0, wr_word_adr} <= wr_word_adr + 1;
                                        wr_word_data <= {wr_word_data[14:0], wr_word_data[15]};
                                        wr_state = 0;
                                        delay = 0;
                                end
                        end
                        endcase
        end
end

// *** ASSIGNMENTS ***

assign d[15:0] = ((otkl & module_enable) | ~module_enable) ? 16'hZZZZ : data;
assign a[20:1] = adr[19:0];

assign flash_ce_b = t_flash_ce_b;

assign oe_b = t_oe_b;
assign we_b = t_we_b;

wire wr0_rdy;
edge_detector wr0_re(
        .clk(clk),
        .reset_b(resetb_b),
        .i(stop_writing_0),
        .rise_edge(wr0_rdy),
        .fall_edge(null)
);
wire wr1_rdy;
edge_detector wr1_re(
        .clk(clk),
        .reset_b(resetb_b),
        .i(stop_writing_1),
        .rise_edge(wr1_rdy),
        .fall_edge(null)
);

wire erase1_rdy;
edge_detector erase1_re(
        .clk(clk),
        .reset_b(resetb_b),
        .i(stop_erasing_1),
        .rise_edge(erase1_rdy),
        .fall_edge(null)
);
wire erase2_rdy;
edge_detector erase2_re(
        .clk(clk),
        .reset_b(resetb_b),
        .i(stop_erasing_2),
        .rise_edge(erase2_rdy),
        .fall_edge(null)
);

wire [47:0] err_str;
bin2hexchar bh0 (err_cnt[3:0], err_str[7:0]);
bin2hexchar bh1 (err_cnt[7:4], err_str[15:8]);
bin2hexchar bh2 (err_cnt[11:8], err_str[23:16]);
bin2hexchar bh3 (err_cnt[15:12], err_str[31:24]);
bin2hexchar bh4 (err_cnt[19:16], err_str[39:32]);
bin2hexchar bh5 (err_cnt[23:20], err_str[47:40]);

assign ready = wr0_rdy | wr1_rdy | erase1_rdy | erase2_rdy;

/*wire [7:0] glegle;
bin2hexchar bh6 ({stop_erasing_1, stop_erasing_2, stop_writing_1, stop_writing_0}, glegle);

assign string = {": ", glegle, "             "};
*/
assign string = (ERASE1) ? "...erasing 1    " :
                                (WRITE1) ? "...testing run1 " :
                                (ERASE2) ? "...erasing 2    " :
                                (WRITE2) ? "...testing run0 " :
                                (stop_erasing_1 & stop_writing_1 & stop_erasing_2 & stop_writing_0 & (err_cnt == 0)) ? "OK              " : {"0x", err_str, " errors "};

endmodule

module bin2hexchar (bin, char);
input  [3:0] bin;
output [7:0] char;
reg    [7:0] hexchar;
always
        case (bin)
        0: hexchar = "0";
        1: hexchar = "1";
        2: hexchar = "2";
        3: hexchar = "3";
        4: hexchar = "4";
        5: hexchar = "5";
        6: hexchar = "6";
        7: hexchar = "7";
        8: hexchar = "8";
        9: hexchar = "9";
        10: hexchar = "A";
        11: hexchar = "B";
        12: hexchar = "C";
        13: hexchar = "D";
        14: hexchar = "E";
        15: hexchar = "F";
        default: hexchar = "?";
        endcase
assign char = hexchar;
endmodule