manage_registers.v

ethmac10g_latest.tar.gz源代码

	      fragment_frame <=#TP 0;
	   else if(rxStatRegPlus[17])
         fragment_frame <=#TP fragment_frame + 1;
end //num of fragment frames 

always@(posedge rxclk or posedge reset) begin
      if (reset)
	      total_bytes_recved <=#TP 0;
	   else if(rxStatRegPlus[18])
         total_bytes_recved <=#TP total_bytes_recved + 1;
end //bytes have been received

//--Transmit Related
always@(posedge txclk or posedge reset) begin
      if (reset)
	      total_bytes_transed <=#TP 0;
	   else if(txStatRegPlus[0])
         total_bytes_transed <=#TP total_bytes_transed + 1;
end //bytes have been transmitted

always@(posedge txclk or posedge reset) begin
      if (reset)
	      good_frame_transed <=#TP 0;
	   else if(txStatRegPlus[1])
         good_frame_transed <=#TP good_frame_transed + 1;
end //num of error free frames have been transmitted

always@(posedge txclk or posedge reset) begin
      if (reset)
	      broadcast_frame_transed <=#TP 0;
	   else if(txStatRegPlus[2])
         broadcast_frame_transed <=#TP broadcast_frame_transed + 1;
end //num of broadcast frames have been transmitted

always@(posedge txclk or posedge reset) begin
      if (reset)
	      multicast_frame_transed <=#TP 0;
	   else if(txStatRegPlus[3])
         multicast_frame_transed <=#TP multicast_frame_transed + 1;
end //num of multicast frames have been transmitted

always@(posedge txclk or posedge reset) begin
      if (reset)
	      underrun_error <=#TP 0;
	   else if(txStatRegPlus[4])
         underrun_error <=#TP underrun_error + 1;
end //num of underrun error frames have been transmitted

always@(posedge txclk or posedge reset) begin
      if (reset)
	      control_frame_transed <=#TP 0;
	   else if(txStatRegPlus[5])
         control_frame_transed <=#TP control_frame_transed + 1;
end //num of control frames have been transmitted

always@(posedge txclk or posedge reset) begin
      if (reset)
	      frame_64_transed <=#TP 0;
	   else if(txStatRegPlus[6])
         frame_64_transed <=#TP frame_64_transed + 1;
end //num of frames have been transmitted, with length equal 64

always@(posedge txclk or posedge reset) begin
      if (reset)
	      frame_65_127_transed <=#TP 0;
	   else if(txStatRegPlus[7])
         frame_65_127_transed <=#TP frame_65_127_transed + 1;
end //num of frames have been transmitted, with length are between 65 and 127

always@(posedge txclk or posedge reset) begin
      if (reset)
	      frame_128_255_transed <=#TP 0;
	   else if(txStatRegPlus[8])
         frame_128_255_transed <=#TP frame_128_255_transed + 1;
end //num of frames have been transmitted, with length are between 128 and 255

always@(posedge txclk or posedge reset) begin
      if (reset)
	      frame_256_511_transed <=#TP 0;
	   else if(txStatRegPlus[9])
         frame_256_511_transed <=#TP frame_256_511_transed + 1;
end //num of frames have been transmitted, with length are between 256 and 511

always@(posedge txclk or posedge reset) begin
      if (reset)
	      frame_512_1023_transed <=#TP 0;
	   else if(txStatRegPlus[10])
         frame_512_1023_transed <=#TP frame_512_1023_transed + 1;
end //num of frames have been transmitted, with length are between 512 and 1023

always@(posedge txclk or posedge reset) begin
      if (reset)
	      frame_1024_max_transed <=#TP 0;
	   else if(txStatRegPlus[11])
         frame_1024_max_transed <=#TP frame_1024_max_transed + 1;
end //num of frames have been transmitted, with length are between 1024 and max length

always@(posedge txclk or posedge reset) begin
      if (reset)
	      tagged_frame_transed <=#TP 0;
	   else if(txStatRegPlus[12])
         tagged_frame_transed <=#TP tagged_frame_transed + 1;
end //num of tagged frames have been transmitted

always@(posedge txclk or posedge reset) begin
      if (reset)
	      pause_frame_transed <=#TP 0;
	   else if(txStatRegPlus[13])
         pause_frame_transed <=#TP pause_frame_transed + 1;
end //num of pause frames have been transmitted

always@(posedge txclk or posedge reset) begin
      if (reset)
	      oversize_frame_transed <=#TP 0;
	   else if(txStatRegPlus[14])
         oversize_frame_transed <=#TP oversize_frame_transed + 1;
end //num of frames whose length are larger than max length

/////////////////////////////////////////////
// Read Statistics Registers
/////////////////////////////////////////////
reg[63:0] stat_rd_data;
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
		  stat_rd_data <=#TP 0;
      else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9])begin
		  case (mgmt_addr[7:0])
		      8'h00: stat_rd_data <= frame_received_good;
		      8'h01: stat_rd_data <= fcs_error;
		      8'h02: stat_rd_data <= broadcast_received_good;
		      8'h03: stat_rd_data <= multicast_received_good;
		      8'h04: stat_rd_data <= frame_64_good;
		      8'h05: stat_rd_data <= frame_65_127_good;
		      8'h06: stat_rd_data <= frame_128_255_good;
		      8'h07: stat_rd_data <= frame_256_511_good;
		      8'h08: stat_rd_data <= frame_512_1023_good;
		      8'h09: stat_rd_data <= frame_1024_max_good;
		      8'h0a: stat_rd_data <= control_frame_good;
		      8'h0b: stat_rd_data <= lt_out_range;
		      8'h0c: stat_rd_data <= tagged_frame_good;
		      8'h0d: stat_rd_data <= pause_frame_good;
		      8'h0e: stat_rd_data <= unsupported_control_frame;
		      8'h0f: stat_rd_data <= oversize_frame_good;
		      8'h10: stat_rd_data <= undersize_frame;
		      8'h11: stat_rd_data <= fragment_frame;
		      8'h12: stat_rd_data <= total_bytes_recved;
		      8'h13: stat_rd_data <= total_bytes_transed;
		      8'h20: stat_rd_data <= good_frame_transed;
		      8'h21: stat_rd_data <= broadcast_frame_transed;
		      8'h22: stat_rd_data <= multicast_frame_transed;
		      8'h23: stat_rd_data <= underrun_error;
		      8'h24: stat_rd_data <= control_frame_transed;
		      8'h25: stat_rd_data <= frame_64_transed;
		      8'h26: stat_rd_data <= frame_65_127_transed;
		      8'h27: stat_rd_data <= frame_128_255_transed;
		      8'h28: stat_rd_data <= frame_256_511_transed;
		      8'h29: stat_rd_data <= frame_512_1023_transed;
		      8'h2a: stat_rd_data <= frame_1024_max_transed;
		      8'h2b: stat_rd_data <= tagged_frame_transed;
		      8'h2c: stat_rd_data <= pause_frame_transed;
		      8'h2d: stat_rd_data <= oversize_frame_transed;
            default: stat_rd_data <= 0;
       endcase
    end
end	 
 
////////////////////////////////////////////////////////
// READ Statmachine
//
// Select which data to be writen to mgmt_rd_data
////////////////////////////////////////////////////////
reg[31:0] mgmt_rd_data;
reg mgmt_miim_rdy;
reg data_sel;
always@(posedge mgmt_clk or posedge reset) begin
      if(reset) begin
         mgmt_rd_data <=#TP 0;
			data_sel <=#TP 0; //0 select the lower 32bits of stat regs to mgmt_rd_data, while 1 select the higher 32bits
			read_done <=#TP 0; // when asserted, it indicates read operation has been finished
			mgmt_miim_rdy <=#TP 0;
		end	
		else begin
         case (state)
			    IDLE: begin
				     mgmt_rd_data <=#TP mgmt_rd_data;
				     data_sel <=#TP 1'b0;
			        read_done <=#TP 0;
			        mgmt_miim_rdy <=#TP 1;
					  if(mgmt_req & mgmt_miim_sel)
					    mgmt_miim_rdy <=#TP 0;
				 end
             STAT_OPERATE: begin // read statistics registers
				     mgmt_miim_rdy <=#TP 1;
			        read_done <=#TP 1'b0;
                 if (~data_sel) begin						
			          mgmt_rd_data <=#TP stat_rd_data[31:0];
					    data_sel <=#TP 1'b1;
					  end
					  else if(data_sel)begin
					    mgmt_rd_data <=#TP stat_rd_data[63:32];
						 data_sel <=#TP 1'b0;
			          read_done <=#TP 1'b1;
					  end 
				 end
				 CONFIG_OPERATE: begin // read configuration registers
				     case (mgmt_addr_d1[8:4])
					        5'h00: mgmt_rd_data <=#TP recv_config0;
                       5'h04: mgmt_rd_data <=#TP recv_config1;
                       5'h08: mgmt_rd_data <=#TP trans_config;
                       5'h0c: mgmt_rd_data <=#TP flow_control_config;
                       5'h10: mgmt_rd_data <=#TP rs_config;	
                       5'h14: mgmt_rd_data <=#TP mgmt_config;
							  default: mgmt_rd_data <=#TP mgmt_rd_data;
					  endcase
				 end	  
             MDIO_OPERATE: begin // read/write MDIO registers
				     if(~mdio_in_valid & mdio_in_valid_d1) begin
                    mgmt_rd_data[15:0] <=#TP mdio_data_in;
						  mgmt_rd_data[31:16] <=#TP 0;
						  mgmt_miim_rdy <=#TP 1'b1;
					  end
                 else begin
                    mgmt_rd_data <=#TP mgmt_rd_data;
						  mgmt_miim_rdy <=#TP 1'b0;
                 end						  
             end	
             default: begin
                 mgmt_rd_data <=#TP 0;
			        data_sel <=#TP 0;
			        read_done <=#TP 0;
		           mgmt_miim_rdy <=#TP 1;
             end	
          endcase
      end	
end		 

/////////////////////////////////////////////
// Write Configuration Registers
/////////////////////////////////////////////
reg[31:0] mgmt_wr_data_d1;
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
		   mgmt_wr_data_d1 <=#TP 0;
		else
		   mgmt_wr_data_d1 <=#TP mgmt_wr_data;
end

always@(posedge mgmt_clk or posedge reset)begin
      if(reset)begin
		  recv_config0 <=#TP 0;
        recv_config1 <=#TP 32'h10000000;
        trans_config <=#TP 32'h10000000;
        flow_control_config <=#TP 32'h60000000;
        rs_config <=#TP 0;
        mgmt_config <=#TP 32'h00100000;
		end
      else if(~mgmt_miim_sel & mgmt_addr[9]& ~mgmt_opcode[1]) begin // write configuration registers
        case (mgmt_addr[8:0]) 
          9'h000: recv_config0 <=#TP mgmt_wr_data;
          9'h040: recv_config1 <=#TP mgmt_wr_data;
          9'h080: trans_config <=#TP mgmt_wr_data;
          9'h0c0: flow_control_config <=#TP mgmt_wr_data;
          9'h100: rs_config <=#TP mgmt_wr_data;	
          9'h140: mgmt_config <=#TP mgmt_wr_data;
			 default: begin
			   recv_config0 <=#TP recv_config0;
            recv_config1 <=#TP recv_config1;
            trans_config <=#TP trans_config;
            flow_control_config <=#TP flow_control_config;
            rs_config <=#TP rs_config;
            mgmt_config <=#TP mgmt_config;
			 end	
        endcase
      end
end
		
///////////////////////////////////////////////////////
// Read Configuration Registers, 
// generates receive and transmit configuration vector
///////////////////////////////////////////////////////

assign cfgRxRegData = {recv_config1[31:27], recv_config1[15:0], recv_config0};
assign cfgTxRegData = {rs_config[27], trans_config[31:24],flow_control_config[30]}; 

///////////////////////////////////////////////
// Interface with MDIO module
// Generate control and data signals for MDIO
///////////////////////////////////////////////
reg[25:0] mdio_data_out; //output data, includes PHY address and data to be writen
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
		   mdio_data_out <=#TP 0;
		else if(mgmt_req & mgmt_miim_sel)
		   mdio_data_out <=#TP {mgmt_addr[9:0], mgmt_wr_data[15:0]};
		else
		   mdio_data_out <=#TP mdio_data_out;
end

reg[1:0] mdio_opcode; //MDIO operation code, 2'b10 is read, while 2'b01 is write
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
		  mdio_opcode <=#TP 0;
		else if(mgmt_req & mgmt_miim_sel)
		  mdio_opcode <=#TP mgmt_opcode;
end

reg[4:0] tmp_cnt; //used to longer the mdio_out_valid signal
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
		   tmp_cnt <=#TP 0;
		else if(mgmt_req & mgmt_miim_sel)
		   tmp_cnt <=#TP 0;
		else if(tmp_cnt == 30)
		   tmp_cnt <=#TP tmp_cnt;
		else	
		   tmp_cnt <=#TP tmp_cnt + 1;
end			

reg mdio_out_valid; //indicates a MDIO request is valid, lasts for 31 cycles(mgmt_clk)
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
			mdio_out_valid <=#TP 0;
		else if(mgmt_req & mgmt_miim_sel) 
		   mdio_out_valid <=#TP 1'b1;
		else if(tmp_cnt ==30)
		   mdio_out_valid <=#TP 1'b0;
		else
         mdio_out_valid <= #TP mdio_out_valid;		
end		

endmodule