manage_registers.v

ethmac10g_latest.tar.gz源代码

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// MODULE NAME: manage_registers                                ////
////                                                              ////
//// DESCRIPTION: implement read & write logic for configuration  ////
////              and statistics registers                        ////
////                                                              ////
//// This file is part of the 10 Gigabit Ethernet IP core project ////
////  http://www.opencores.org/projects/ethmac10g/                ////
////                                                              ////
//// AUTHOR(S):                                                   ////
//// Zheng Cao                                                    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (c) 2005 AUTHORS.  All rights reserved.            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS REVISION HISTORY:
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2006/06/15 12:12:27  fisher5090
// modify mgmt_miim_rdy timing sequence
//
// Revision 1.3  2006/06/15 08:25:42  fisher5090
// comments added
//
// Revision 1.2  2006/06/15 05:09:24  fisher5090
// bad coding style, but works, will be modified later
//
// Revision 1.1  2005/12/25 16:43:10  Zheng Cao
// 
// 
//
//////////////////////////////////////////////////////////////////////
module manage_registers(mgmt_clk, rxclk, txclk, reset, mgmt_opcode, mgmt_addr, mgmt_wr_data, mgmt_rd_data, mgmt_miim_sel, mgmt_req, 
mgmt_miim_rdy, rxStatRegPlus, txStatRegPlus, cfgRxRegData, cfgTxRegData, mdio_opcode, mdio_data_out, mdio_data_in, mdio_in_valid,
mgmt_config, mdio_out_valid);
input mgmt_clk; //management clock
input rxclk; //receive clock
input txclk; //transmit clock
input reset; //system reset
input[1:0] mgmt_opcode; //management opcode(read/write/mdio)
input[9:0] mgmt_addr; //management address, including addresses of configuration, statistics and MDIO registers
input[31:0] mgmt_wr_data; //Data to be writen to Configuration/MDIO registers
output[31:0] mgmt_rd_data; //Data read from Configuration/Statistics/MDIO registers
input mgmt_miim_sel; //select internal register or MDIO registers
input mgmt_req; //Valid when operate statistics/MDIO registers, one clock valid____|-|____
output mgmt_miim_rdy; //Indicate the Management Module is in IDLE Status
input[18:0] rxStatRegPlus; //From Receive Module, one bit is related to one receive statistics register
input[14:0] txStatRegPlus; //From Transmit Module, one bit is related to one transmit statistics register
output[52:0] cfgRxRegData; //To Receive Module, config receive module
output[9:0] cfgTxRegData; //To Transmit Module, config transmit module
output[1:0] mdio_opcode; //MDIO Opcode, equals mgmt_opcode
output mdio_out_valid; //Indicate mdio_data_out is valid
output[25:0] mdio_data_out; //Data to be writen to MDIO, {addr, data}
input[15:0] mdio_data_in; //Data read from MDIO
input mdio_in_valid; //Indicate mdio_data_in read from MDIO is valid
output[31:0] mgmt_config; //management configuration data, mainly used to set mdc frequency

parameter IDLE =0, MDIO_OPERATE =1, STAT_OPERATE =2, CONFIG_OPERATE =3;
parameter TP = 1;

/////////////////////////////////////////////
// Statistics Register Definition
/////////////////////////////////////////////

//--Receive Related
reg[63:0] frame_received_good;
reg[63:0] fcs_error;
reg[63:0] broadcast_received_good;
reg[63:0] multicast_received_good;
reg[63:0] frame_64_good;
reg[63:0] frame_65_127_good;
reg[63:0] frame_128_255_good;
reg[63:0] frame_256_511_good;
reg[63:0] frame_512_1023_good;
reg[63:0] frame_1024_max_good;
reg[63:0] control_frame_good;
reg[63:0] lt_out_range;
reg[63:0] tagged_frame_good;
reg[63:0] pause_frame_good;
reg[63:0] unsupported_control_frame;
reg[63:0] oversize_frame_good;
reg[63:0] undersize_frame;
reg[63:0] fragment_frame;
reg[63:0] total_bytes_recved;

//--Transmit Related
reg[63:0] total_bytes_transed;
reg[63:0] good_frame_transed;
reg[63:0] broadcast_frame_transed;
reg[63:0] multicast_frame_transed;
reg[63:0] underrun_error;
reg[63:0] control_frame_transed;
reg[63:0] frame_64_transed;
reg[63:0] frame_65_127_transed;
reg[63:0] frame_128_255_transed;
reg[63:0] frame_256_511_transed;
reg[63:0] frame_512_1023_transed;
reg[63:0] frame_1024_max_transed;
reg[63:0] tagged_frame_transed;
reg[63:0] pause_frame_transed;
reg[63:0] oversize_frame_transed;

/////////////////////////////////////////////
// Configuration Registers Definition
/////////////////////////////////////////////

reg[31:0] recv_config0;
reg[31:0] recv_config1;
reg[31:0] trans_config;
reg[31:0] flow_control_config;
reg[31:0] rs_config;
reg[31:0] mgmt_config;

/////////////////////////////////////////////
// Input registers
/////////////////////////////////////////////

reg[8:0] mgmt_addr_d1;
always@(posedge mgmt_clk or posedge reset)begin
      if(reset)
		  mgmt_addr_d1 <=#TP 0;
		else 
		  mgmt_addr_d1 <=#TP mgmt_addr[8:0];
end

reg mdio_in_valid_d1;
always@(posedge mgmt_clk or posedge reset) begin
      if(reset)
		  mdio_in_valid_d1 <=#TP 1'b0;
		else 
		  mdio_in_valid_d1 <=#TP mdio_in_valid;
end		 

/////////////////////////////////////////////
// State Machine
/////////////////////////////////////////////
reg[1:0] state;
reg read_done;
always@(posedge mgmt_clk or posedge reset)begin
    if (reset)
	    state <=#TP IDLE;
	 else begin
	    case (state)
		    IDLE: begin
			     if(mgmt_req & mgmt_miim_sel) // MDIO Operations
				    state <=#TP MDIO_OPERATE;
				  else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9]) // Operations on Statistics registers 
				    state <=#TP STAT_OPERATE;
				  else if(~mgmt_miim_sel & mgmt_addr[9]) // Operations on Configuration registers
				    state <=#TP CONFIG_OPERATE;
				  else
				    state <=#TP IDLE;
			 end
          MDIO_OPERATE: begin
              if(~mdio_in_valid & mdio_in_valid_d1) // MDIO read/write done
                state <=#TP IDLE;
              else
                state <=#TP MDIO_OPERATE;
          end					
          STAT_OPERATE: begin 
              if(read_done) // for statistics registers, only read operation happens 
                state <=#TP IDLE;
              else
                state <=#TP STAT_OPERATE;
          end
          CONFIG_OPERATE: begin
              if(mgmt_req & mgmt_miim_sel) //during operation on configuration registers, 
                                           //other request can be responsed. because such 
	                                   //operations only take one cycle time.  
		state <=#TP MDIO_OPERATE
   	      else if(~mgmt_miim_sel & mgmt_req & ~mgmt_addr[9]) 
	        state <=#TP STAT_OPERATE;
	      else if(~mgmt_miim_sel & mgmt_addr[9])
	        state <=#TP CONFIG_OPERATE;
	     else
     	        state <=#TP IDLE;
          end
      endcase
   end
end	

/////////////////////////////////////////////
// Write Statistics Registers
/////////////////////////////////////////////

//--Receive Related
always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_received_good <=#TP 1;
      else if(rxStatRegPlus[0])
         frame_received_good <=#TP frame_received_good + 1;
end // num of good frames have been received

always@(posedge rxclk or posedge reset) begin
      if (reset)
         fcs_error <=#TP 2;
      else if(rxStatRegPlus[1])
         fcs_error <=#TP fcs_error + 1;
end // num of frames that have failed in FCS checking

always@(posedge rxclk or posedge reset) begin
      if (reset)
         broadcast_received_good <=#TP 0;
      else if(rxStatRegPlus[2])
         broadcast_received_good <=#TP broadcast_received_good + 1;
end // num of broadcast frames that have been successfully received

always@(posedge rxclk or posedge reset) begin
      if (reset)
         multicast_received_good <=#TP 0;
      else if(rxStatRegPlus[3])
         multicast_received_good <=#TP multicast_received_good + 1;
end // num of multicast frames that have been successfully received

always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_64_good <=#TP 0;
      else if(rxStatRegPlus[4])
         frame_64_good <=#TP frame_64_good + 1;
end //num of frames that have been successfully received, with length equal to 64

always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_65_127_good <=#TP 0;
      else if(rxStatRegPlus[5])
         frame_65_127_good <=#TP frame_65_127_good + 1;
end //num of frames that have been successfully received, with length between 65 and 127

always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_128_255_good <=#TP 0;
      else if(rxStatRegPlus[6])
         frame_128_255_good <=#TP frame_128_255_good + 1;
end //num of frames that have been successfully received, with length between 128 and 255

always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_256_511_good <=#TP 0;
      else if(rxStatRegPlus[7])
         frame_256_511_good <=#TP frame_256_511_good + 1;
end //num of frames that have been successfully received, with length between 256 and 511

always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_512_1023_good <=#TP 0;
      else if(rxStatRegPlus[8])
         frame_512_1023_good <=#TP frame_512_1023_good + 1;
end //num of frames that have been successfully received, with length between 512 and 1023

always@(posedge rxclk or posedge reset) begin
      if (reset)
         frame_1024_max_good <=#TP 0;
      else if(rxStatRegPlus[9])
         frame_1024_max_good <=#TP frame_1024_max_good + 1;
end //num of frames that have been successfully received, with length between 1024 and max length

always@(posedge rxclk or posedge reset) begin
      if (reset)
	      control_frame_good <=#TP 0;
	   else if(rxStatRegPlus[10])
         control_frame_good <=#TP control_frame_good + 1;
end //num of control frames that have been successfully received

always@(posedge rxclk or posedge reset) begin
      if (reset)
	      lt_out_range <=#TP 0;
	   else if(rxStatRegPlus[11])
         lt_out_range <=#TP lt_out_range + 1;
end //num of frames whose length are too large

always@(posedge rxclk or posedge reset) begin
      if (reset)
	      tagged_frame_good <=#TP 0;
	   else if(rxStatRegPlus[12])
         tagged_frame_good <=#TP tagged_frame_good + 1;
end //num of tagged frames that have been successfully received

always@(posedge rxclk or posedge reset) begin
      if (reset)
	      pause_frame_good <=#TP 0;
	   else if(rxStatRegPlus[13])
         pause_frame_good <=#TP pause_frame_good + 1;
end //num of pause frames that have been successfully received

always@(posedge rxclk or posedge reset) begin
      if (reset)
	      unsupported_control_frame <=#TP 0;
	   else if(rxStatRegPlus[14])
         unsupported_control_frame <=#TP unsupported_control_frame + 1;
end //num of frames whose type filed haven't been defined in IEEE 802.3*

always@(posedge rxclk or posedge reset) begin
      if (reset)
	      oversize_frame_good <=#TP 0;
	   else if(rxStatRegPlus[15])
         oversize_frame_good <=#TP oversize_frame_good + 1;
end //num of frames which are good, only with large size

always@(posedge rxclk or posedge reset) begin
      if (reset)
	      undersize_frame <=#TP 0;
	   else if(rxStatRegPlus[16])
         undersize_frame <=#TP undersize_frame + 1;
end //num of frames whose length are too short

always@(posedge rxclk or posedge reset) begin
      if (reset)