transmittop.v

ethmac10g_latest.tar.gz源代码

    FRAME_START <= 1;
  end
  else if ((TX_DATA_VALID_REG != 8'hff) & (BYTE_COUNTER != 0)) begin
    FRAME_START <= 0;
  end
end




assign reset_int = RESET;


//TXSTATREGPLUS[24:0]
//24 pause_frame transmitted - count when pause flag is set
//23 to 20 bytes valid
//19 vlan frame - asserted if previous frame was a VLAN - just check if VLAN been set
//18 to 5 last frame length count in bytes stick to 16383 when jumbo frame is greater than value - just load the byte count
//4 if last frame has control type code 88-08 in the length type field - pause frame - check if pause flag is set
//3 underrun frame - check if underrun is set
//2 multicast frame - 01-80-C2-00-00-01 use for pause frame
//1 broadcast frame - al ones  
//0 sucessful frame - check if error occurred -use insert error flag


//TX_STATS_VALID - need to be driving after a frame transmission - use load_overflow signal


always @(posedge TX_CLK or posedge reset_int)
begin 
  if (reset_int) begin
    txstatplus_int <= 0;
  end
  else if (load_final_CRC) begin
    if (insert_error) begin
      txstatplus_int[3] <= 1;
    end
    if (set_pause_stats) begin
      txstatplus_int[24] <= 1;
      txstatplus_int[4] <= 1;
      txstatplus_int[2] <= 1;
      txstatplus_int[1] <= 1;
      txstatplus_int[18:5] <= 512;
    end
    if (vlan_enabled_int) begin
      txstatplus_int[19] <= 1;
    end
    else begin
      if (final_byte_count[15] == 1) begin
        txstatplus_int[18:5] <= 16383;
      end
      else begin
        txstatplus_int[18:5] <= byte_count_stat;
      end
    end
  end
  else begin
    txstatplus_int <= 0;
  end
end

always @(posedge TX_CLK)
begin 
  TXSTATREGPLUS <= txstatplus_int;
  TX_STATS_VALID <= append_end_frame;
end


//input [31:0] TX_CFG_REG_VALUE;
//24:0 reserved
//25 default to 0 - min frame  - 1 adjust frame delay by reading inter-frame gap delay reg - DELAY_ACK signal
//26 WAN - not used
//27 VLAN enable default to 0, 1 enabled
//28 default to 1 - transmitter enbaled, 0 - transmitter disabled - possibly used to reset
//29 default to 0 FCS enabled, 1 FCS disabled
//30 default to 0,  1 - Jumbo frame enabled
//31 deafult to 0, 1 - reset transmitter

//input TX_CFG_REG_VALID;

always @(posedge TX_CLK or posedge reset_int)
begin 
  if (reset_int) begin
    vlan_enabled_int <= 0;
    jumbo_enabled_int <= 0;
    tx_enabled_int <= 0;
    fcs_enabled_int <= 1;
    reset_tx_int <= 0;
    read_ifg_int <= 0;
  end
  else if (TX_CFG_REG_VALID) begin
    vlan_enabled_int <= TX_CFG_REG_VALUE[27];
    jumbo_enabled_int <= TX_CFG_REG_VALUE[30];
    tx_enabled_int <= TX_CFG_REG_VALUE[28]; // Stop ack from generated, hold reset
    fcs_enabled_int <= TX_CFG_REG_VALUE[29];
    reset_tx_int <= TX_CFG_REG_VALUE[31]; 
    read_ifg_int <= TX_CFG_REG_VALUE[25];
  end
end


//Load the delay value for the acknowledge signal
always @(posedge TX_CLK or posedge reset_int)
begin
   if (reset_int) begin
     DELAY_ACK <= 16'h0001;
   end
   else if (apply_pause_delay) begin
     DELAY_ACK <= store_pause_frame;
   end
   else if (read_ifg_int) begin
     DELAY_ACK <= TX_IFG_DELAY;
   end
 end


//Need to expand to be setup by the config register
//1514 with out FCS added, 1518 when FCS is added
//1518 without FCS added, 1522 when FCS is added
always @(posedge TX_CLK or posedge reset_int)
begin
  if (reset_int) begin
    MAX_FRAME_SIZE <= 1514;
  end
  else begin
    if (vlan_enabled_int) begin
      if (fcs_enabled_int) begin
        MAX_FRAME_SIZE <= 1522;
      end
      else begin
        MAX_FRAME_SIZE <= 1518;
      end
    end
    else if (jumbo_enabled_int) begin
     if (fcs_enabled_int) begin
        MAX_FRAME_SIZE <= 1518;
      end
      else begin
        MAX_FRAME_SIZE <= 1514;
      end
    end
    else begin
      if (fcs_enabled_int) begin
        MAX_FRAME_SIZE <= 1518;
      end
      else begin
        MAX_FRAME_SIZE <= 1514;
      end
    end
  end
end




always @(posedge TX_CLK)
begin
  if (reset_int) begin
    tx_undderrun_int <= 0;
  end
  else if (append_end_frame)begin
    tx_undderrun_int <= 0;
  end
  else if (TX_UNDERRUN) begin
    tx_undderrun_int <= 1;
  end
end

//Indicate an error
always @(posedge TX_CLK or posedge reset_int)
begin
  if (reset_int) begin
     insert_error <= 0;
  end
  else if (append_end_frame | reset_err_pause) begin
     insert_error <= 0;
  end
  else if (load_CRC8) begin
 	if (tx_undderrun_int == 1) begin
	  insert_error <= 1;	
	end
	else begin
	  if (length_register == final_byte_count) begin
	    if (final_byte_count <= MAX_FRAME_SIZE) begin
     	      insert_error <= 0;
          end
          else begin
            insert_error <= 1;
          end
        end
        else if (length_register < MIN_FRAME_SIZE) begin
          if (final_byte_count == 64) begin
            insert_error <= 0;
          end
          else begin
            insert_error <= 1;
          end
        end
        else begin
          insert_error <= 1;
        end
     end
  end
end


//use for delaying the ack signal when pause is required
always @(posedge TX_CLK or posedge reset_int)
begin
   if (reset_int) begin
     apply_pause_delay <= 0;
     store_pause_frame <= 0;
   end
   else if (TX_ACK) begin
     apply_pause_delay <= 0;
     store_pause_frame <= 0;
   end
   else if (FC_TX_PAUSEVALID) begin
     apply_pause_delay <= 1;
     store_pause_frame <= FC_TX_PAUSEDATA;
   end
end




always @(posedge TX_CLK)
begin
  if (TX_START) begin
    TX_DATA_VALID_DELAY <= IDLE_FRAME_8BYTES;
  end
  else begin
    TX_DATA_VALID_DELAY <= TX_DATA;
  end
end



//Shift valid into the system and also ensuring min frame is achieved
always @(posedge TX_CLK or posedge reset_int)
begin
  if (reset_int) begin   
   TX_DATA_VALID_REG <= 0;
  end
  else if (FRAME_START) begin
   if (BYTE_COUNTER < 48) begin
     TX_DATA_VALID_REG <= 8'b11111111;
   end
   else if (BYTE_COUNTER == 48) begin
     if (TX_START) begin
       TX_DATA_VALID_REG <= 8'b00001111;  
     end   
     else begin
       TX_DATA_VALID_REG <= 8'b00001111 | TX_DATA_VALID; 
     end
   end
   else begin
     if (TX_START) begin
       TX_DATA_VALID_REG <= 0;
     end
     else begin
	 TX_DATA_VALID_REG <= TX_DATA_VALID;
     end
   end
  end
  else if (transmit_pause_frame_del) begin
     TX_DATA_VALID_REG <= shift_pause_valid_del;
  end
  else begin
   TX_DATA_VALID_REG <= 0;
  end
end


//Shifting data to the system. Also ensuring min frame is achieved
always @(posedge TX_CLK or posedge reset_int)
begin
  if (reset_int) begin
     TX_DATA_REG <= IDLE_FRAME_8BYTES;
  end
  else if (FRAME_START) begin
     if (BYTE_COUNTER < 56) begin
        case (TX_DATA_VALID_REG)
      	8'b00000000 : begin
                      TX_DATA_REG <= TX_DATA_VALID_DELAY;
                    end
        8'b00000001 : begin
                      TX_DATA_REG <= {56'h00000000000000, TX_DATA_VALID_DELAY[7:0]};
                    end
        8'b00000011 : begin
                      TX_DATA_REG <= {48'h000000000000, TX_DATA_VALID_DELAY[15:0]};
                    end                                                   
      	8'b00000111 : begin
                      TX_DATA_REG <= {40'h0000000000, TX_DATA_VALID_DELAY[23:0]};
                    end
        8'b00001111 : begin
                      TX_DATA_REG <= {32'h00000000, TX_DATA_VALID_DELAY[31:0]};
                    end
        8'b00011111 : begin
                      TX_DATA_REG <= {24'h000000, TX_DATA_VALID_DELAY[39:0]};
                    end    
      	8'b00111111 : begin
                      TX_DATA_REG <= {16'h0000, TX_DATA_VALID_DELAY[47:0]};
                    end
        8'b01111111 : begin
                      TX_DATA_REG <= {8'h00, TX_DATA_VALID_DELAY[55:0]};
                    end
        8'b11111111 : begin
                      TX_DATA_REG <= TX_DATA_VALID_DELAY;
                    end                    
        endcase                          
     end
     else begin
        TX_DATA_REG <= TX_DATA_VALID_DELAY;
     end
  end
  else if (transmit_pause_frame_valid) begin
     TX_DATA_REG <= shift_pause_data;
  end  
  else begin
     if (TX_ACK | append_start_pause) begin
       TX_DATA_REG <= START_SEQ;
     end
     else begin
       TX_DATA_REG <= IDLE_FRAME_8BYTES;
     end
  end

end







//Use for shifting data to CRC and loading start value for CRC
always @(posedge TX_CLK or posedge reset_int)
begin
  if (reset_int) begin
    frame_start_del <= 0;
    transmit_pause_frame_del <= 0;
    transmit_pause_frame_del2 <= 0;
    transmit_pause_frame_del3 <= 0;
    append_start_pause <= 0;
    append_start_pause_del <= 0;
    transmit_pause_frame_valid <= 0;
    reset_err_pause <= 0;
    load_CRC8 <= 0;
  end
  else begin
    frame_start_del <= FRAME_START;
    transmit_pause_frame_del <= transmit_pause_frame;
    transmit_pause_frame_del2 <= transmit_pause_frame_del;
    transmit_pause_frame_del3 <= transmit_pause_frame_del2;
    append_start_pause <= (!transmit_pause_frame_del & transmit_pause_frame);
    append_start_pause_del <= append_start_pause;
    transmit_pause_frame_valid <= (transmit_pause_frame_del & transmit_pause_frame);
    reset_err_pause <= (transmit_pause_frame_del & !transmit_pause_frame);
    load_CRC8 <= (frame_start_del & !FRAME_START) | (transmit_pause_frame_del3 & !transmit_pause_frame_del2);
  end
end



always @(posedge TX_CLK or posedge reset_int)
begin
  if (reset_int) begin
    TX_DATA_VALID_DEL1 <= 0;
    TX_DATA_VALID_DEL2 <= 0;
    TX_DATA_VALID_DEL3 <= 0;
    TX_DATA_VALID_DEL4 <= 0;
    TX_DATA_VALID_DEL5 <= 0;
    TX_DATA_VALID_DEL6 <= 0;
    TX_DATA_VALID_DEL7 <= 0;
    TX_DATA_VALID_DEL8 <= 0;
    TX_DATA_VALID_DEL9 <= 0;
    TX_DATA_VALID_DEL10 <= 0;
    TX_DATA_VALID_DEL11 <= 0;
    TX_DATA_VALID_DEL12 <= 0;
    TX_DATA_VALID_DEL13 <= 0;
    TX_DATA_VALID_DEL14 <= 0;
    TX_DATA_VALID_DEL15 <= 0;
    OVERFLOW_VALID <= 0;
  end
  else begin
    TX_DATA_VALID_DEL1 <= TX_DATA_VALID_REG;
    TX_DATA_VALID_DEL2 <= TX_DATA_VALID_DEL1;
    TX_DATA_VALID_DEL3 <= TX_DATA_VALID_DEL2;
    TX_DATA_VALID_DEL4 <= TX_DATA_VALID_DEL3;
    TX_DATA_VALID_DEL5 <= TX_DATA_VALID_DEL4;
    TX_DATA_VALID_DEL6 <= TX_DATA_VALID_DEL5;
    TX_DATA_VALID_DEL7 <= TX_DATA_VALID_DEL6;
    TX_DATA_VALID_DEL8 <= TX_DATA_VALID_DEL7;
    TX_DATA_VALID_DEL9 <= TX_DATA_VALID_DEL8;
    TX_DATA_VALID_DEL10 <= TX_DATA_VALID_DEL9;
    TX_DATA_VALID_DEL11 <= TX_DATA_VALID_DEL10;
    TX_DATA_VALID_DEL12 <= TX_DATA_VALID_DEL11;
    TX_DATA_VALID_DEL13 <= TX_DATA_VALID_DEL12;
    TX_DATA_VALID_DEL14 <= TX_DATA_VALID_DEL13;

    if (load_final_CRC) begin
    	case (TX_DATA_VALID_DEL13)  
      	8'b00000000 : begin
			    if (fcs_enabled_int) begin
                        TX_DATA_VALID_DEL14 <= 8'b00001111;
                      end
                      else begin
                        TX_DATA_VALID_DEL14 <= 8'b00001111;
                      end
                      OVERFLOW_VALID <= 8'b00000000;     
                    end
      	8'b00000001 : begin
                      if (fcs_enabled_int) begin
    		            TX_DATA_VALID_DEL14 <= 8'b00011111;
                      end
                      
                      OVERFLOW_VALID <= 8'b00000000;		      
                    end
      	8'b00000011 : begin
			    if (fcs_enabled_int) begin
                        TX_DATA_VALID_DEL14 <= 8'b00111111;
                      end		          
                      OVERFLOW_VALID <= 8'b00000000;                
                    end
      	8'b00000111 : begin
                      if (fcs_enabled_int) begin
                        TX_DATA_VALID_DEL14 <= 8'b01111111;
                      end
		          
                      OVERFLOW_VALID <= 8'b00000000;
 			                        
                    end
      	8'b00001111 : begin
			    if (fcs_enabled_int) begin
   	                  TX_DATA_VALID_DEL14 <= 8'b11111111;
                      end

                      OVERFLOW_VALID <= 8'b00000000;
                      
                    end
      	8'b00011111 : begin
                      if (fcs_enabled_int) begin
                        TX_DATA_VALID_DEL14 <= 8'b11111111;
                        OVERFLOW_VALID <= 8'b00000001;
	                end
                      else begin
                        OVERFLOW_VALID <= 8'b00000000;
                      end  
                                          
                    end
      	8'b00111111 : begin
                      if (fcs_enabled_int) begin
   		            TX_DATA_VALID_DEL14 <= 8'b11111111;
                        OVERFLOW_VALID <= 8'b00000011;		            
                      end
                      else begin
                        OVERFLOW_VALID <= 8'b00000000;                       
                      end  
                    end
      	8'b01111111 : begin
                      if (fcs_enabled_int) begin
                        TX_DATA_VALID_DEL14 <= 8'b11111111;
                        OVERFLOW_VALID <= 8'b00000111;
                      end
                      else begin
                        OVERFLOW_VALID <= 8'b00000000;
			    end  
                   end
      	endcase