muxalu2.vhd

来自「自己刚写的一个RISC的cpu」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned.all;

entity muxalu2 is
       port(muxalu2_c:in std_logic;
            --muxalu2_rs:in std_logic;
            muxalu2_rt:in std_logic;
            muxalu2_out:out std_logic
            );
end muxalu2;

architecture one of muxalu2 is
  begin
    process(muxalu2_rt,muxalu2_c)
    begin
      case muxalu2_c is
          when '0'=>
                muxalu2_out<='0';
          when '1'=>
                muxalu2_out<=muxalu2_rt;
          when others=>
                null;
      end case;
    end process;
 end one;